Hybrid Lattice Reduction Algorithm And Its Implementation On An Sdr Baseband Processor For Lte (original) (raw)

A Simulation on lattice reduction techniques for wireless communication MIMO QAM 64x64 and above

Materials Today: Proceedings, 2021

Abstract In wireless communication system, signal those pass through in transmission and receiving antenna in MIMO (Multi-input multi- output) channel to lattice reduce over a QAM (quadrature-amplitude-modulation) system, which is simulated maximum likelihood (ML) estimation and minimum mean square error (MMSE) . In this paper “A Simulation on Lattice Reduction Techniques for wireless Communication MIMO with QAM 64x64 and above”, here the minimum likelihood (ML) estimation and MMSE for multi-input multi-output (MIMO) channels. Generally, in OFDM (orthogonally frequency division multiplexing) system of a MMSE system completely eliminates interference and the results in suboptimal performance due to noise enhancement in symbol. The main aim simulated MMSE detector that the transmitter must spend within M QAM quadrature- amplitude-modulation () alphabet and the ML, MMSE allow to transmitted signal and remove the interference which comes from in receiver and pass through it. Which is QAM 64x64 above simulated BER (bit error rate) with SNR.

Lattice Reduction

IEEE Signal Processing Magazine, 2011

attice reduction is a powerful concept for solving diverse problems involving point lattices. Signal processing applications where lattice reduction has been successfully used include global positioning system (GPS), frequency estimation, color space estimation in JPEG pictures, and particularly data detection and precoding in wireless communication systems. In this article, we first provide some background on point lattices and then give a tutorial-style introduction to the theoretical and practical aspects of lattice reduction. We describe the most important lattice reduction algorithms and comment on their performance and computational complexity. Finally, we discuss the application of lattice reduction in wireless communications and statistical signal processing. Throughout the article, we point out open problems and interesting questions for future research.

A Comparison of Two Lattice-Reduction-Based Receivers for MIMO Systems

2008 IEEE Sarnoff Symposium, 2008

In this paper, we compare a new practical lattice reduction method, Seysen's algorithm, with the existing LLL lattice reduction approach. Seysen's algorithm considers all vectors in the lattice simultaneously and performs global search for lattice reduction, while the LLL algorithm concentrates on local optimization to produce a reduced lattice We also study their performance, when combined with linear detectors (Zero Forcing, MMSE and extended MMSE), and successive interference cancellation (SIC) detector. For MIMO digital communications, Seysen-based linear detectors achieve the same diversity order as the optimum ML detector. It outperforms the existing LLL-based linear detectors. Moreover, Seysen requires less computational time than the LLL scheme. However, this gap disappears in SIC scenario: Seysen-based SIC detector functions the same as LLL-based one, due to the efficiency of SIC itself.

VLSI Implementation of a Lattice-Reduction Algorithm for Multi-Antenna Broadcast Precoding

2007 IEEE International Symposium on Circuits and Systems, 2007

This paper describes the first VLSI implementation of lattice reduction (LR) aided multi-antenna broadcast precoding with vector perturbation. The considered LR scheme is based on Brun's algorithm for finding integer relations. We analyze its high-level architectural issues, we devise a corresponding low-complexity implementation, and, finally, we develop a suitable VLSI architecture. The resulting circuit provides reference for the true silicon complexity of LR for broadcast precoding with vector perturbation.

A customized lattice reduction multiprocessor for MIMO detection

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015

Lattice reduction (LR) is a preprocessing technique for multiple-input multiple-output (MIMO) symbol detection to achieve better bit error-rate (BER) performance. In this paper, we propose a customized homogeneous multiprocessor for LR. The processor cores are based on transport triggered architecture (TTA). We propose some modification of the popular LR algorithm, Lenstra-Lenstra-Lovász (LLL) for high throughput. The TTA cores are programmed with high level language. Each TTA core consists of several special function units to accelerate the program code. The multiprocessor takes 187 cycles to reduce a single matrix for LR. The architecture is synthesized on 90 nm technology and takes 405 kgates at 210 MHz.

High performance lattice reduction on heterogeneous computing platform

The Journal of Supercomputing, 2014

The lattice reduction (LR) technique has become very important in many engineering fields. However, its high complexity makes difficult its use in real-time applications, especially in applications that deal with large matrices. As a solution, the Modified Block LLL (MB-LLL) algorithm was introduced in [10], where several levels of parallelism were exploited: (i.) coarse-grained parallelism was achieved by applying the block-reduction concept presented in [15] and (ii.) fine-grained parallelism was achieved through the Cost Reduced All-Swap LLL (CR-AS-LLL) algorithm introduced in [10]. In this paper, we present the Cost Reduced MB-LLL (CR-MB-LLL) algorithm, which allows to significantly reduce the computational complexity of the MB-LLL by allowing the relaxation of the first LLL condition while executing the LR of submatrices, resulting in the delay of the GS coefficients update and by using less costly procedures during the boundary checks. The effects of complexity reduction and implementation details are analyzed and discussed for several architectures. A mapping of the CR-MB-LLL on a heterogenenous platform is proposed and it is compared with implementations running on a dynamic parallelism enabled GPU and a multi-core CPU. The mapping on the architecture proposed allows a dynamic scheduling of kernels where the overhead introduced is hidden by the use of several CUDA streams. Results show that the execution time of the CR-MB-LLL algorithm on the heterogeneous platform outperforms the multi-core CPU and it is more efficient than the CR-AS-LLL algorithm in case of large matrices.

An Experimental Comparison of Some LLL-Type Lattice Basis Reduction Algorithms

International Journal of Applied and Computational Mathematics, 2015

In this paper we experimentally compare the performance of the L 2 lattice basis reduction algorithm, whose importance recently became evident, with our own Gram-based lattice basis reduction algorithm, which is a variant of the Schnorr-Euchner algorithm. We conclude with observations about the algorithms under investigation for lattice basis dimensions up to the theoretical limit. We also reexamine the notion of "buffered transformations" and its impact on performance of lattice basis reduction algorithms. We experimentally compare four different algorithms directly in the Sage Mathematics Software: our own algorithm, the L 2 algorithm and "buffered" versions of them resulting in a total of four algorithms.