Analysis of Power, Performance and Area at sub-micron ASIC implementation (original) (raw)

An Optimized Power Performance and Area in ASIC Physical Design

International Journal of Electronics, Electrical and Computational System, 2017

For Moore’s law to continue to be pragmatically valid, new process technologies must provide more than the projected increases in density, chip capacity, chip level performance or, performance vs. power-improvement which has been increasingly difficult to achieve. This paper deals with study and implementation of practices to get better PPA in ASIC physical design which is applicable to all digital circuits, both combinational and sequential. Various Place and Route techniques are used to achieve this using Cadence’s SOCE. The general Place and Route flow involves Floor planning, Power planning, Placement, CTS, Routing, Parasitic extraction, Timing and Power analysis. Apart from these stages, there are intermediate stages which allow for timing optimizations. A reference block is chosen and multiple experiments are performed with flow variations at each of Place and Route stage targeting PPA and frequency of 1.4GHz using 14nm technology. Generalized flow is tweaked to achieve the better PPA. All experimental data captured and concluded.

Algorithms and Architectures for Low Power IC Design

The report describes the work carried out by the Queen's University of Belfast into algorithms and architectures for low power. The work is targeted at detailed power consumption analysis of a number of multiplier structures with respect to aspects such as: data wordlengths; data inputs; data organisation and; number systems. In all cases, the analysis has been carried out on synthesised layout using PowerMillTM. The main focus of work is aimed at producing a mechanism for estimating power consumption at a high level ...

Optimization of device dimensions for high-performance low-power architecture blocks

ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705), 2003

A strategy for the implementation of energy-efficient architecture blocks is proposed. It enables mapping of algorithms to architectures at maximal efficiency based on automized optimization of device dimensions of elementary basic cells. As an example, the design of a highthroughput low-power FIR-filter is described. The effectiveness of the proposed strategy is confirmed by comparison with state-of-the-art filter macros.

A Comparative Analysis of Low Power and Area Efficient Digital Circuit Design

Low power consuming devices are playing a dominant role in the present day VLSI design technology. If the power consumption is less, then the amount of power dissipation is also less. The power dissipation of a device can be reduced by using different low power techniques. In the present paper the performance of 4x1 multiplexer in different low power techniques was analyzed and its power dissipation in those techniques is compared with the conventional CMOS design. Each of these techniques has different advantages depending on their logic of operation. The simulation results show that the proposed techniques have less power dissipation compared to the conventional CMOS with reduction in area also.

Technology Scaling and Low Power Design Techniques

Scaling the feature size of transistor made a remarkable advancement in silicon industry. The demand for power-sensitive design has grown significantly in recent years due to growth in portable applications. The need for power-efficient design techniques is increasing. Various efficient design techniques have been proposed to reduce both dynamic as well as static power in state-of-the-art VLSI applications. In this paper, different circuit design techniques both static and dynamic are discussed that reduce the power consumption.

Design optimization of low-power high-performance DSP building blocks

IEEE Journal of Solid-State Circuits, 2000

In recent years, power dissipation along with silicon area has become the key figure in chip design. The increasing demands on system performance require high-performance digital signal processing (DSP) systems to include dedicated number-crunching units as individually optimized building blocks. The various design methodologies in use stress one of the following figures: power dissipation, throughput, or silicon area. This paper presents a design methodology reducing any combination of cost drivers subject to a specified throughput. As a basic principle, the underlying optimization regards the existing interactions within the design space of a building block. Crucial in such optimization is the proper dimensioning of device sizes in contrast to the common use of minimal dimensions in low-power implementations.

Automated Exploration of the Asic Design Space for Minimum Power-Delay-Area Product at the

2004

Dedicated to my wife Selda, my daughters Hatice Nur, and Zeynep Hannan for their love and support ii ACKNOWLEDGEMENT First of all, I would like to thank Professor Donald W. Bouldin, my advisor, for his guidance, encouragement, support and valuable criticism during this research. I also thank my other committee members, Dr. Michael A. Langston, Dr. Gregory Peterson and Dr. Chandra Tan for their guidance and valuable feedback. I would also like to

Ultra-Low Power Design of Digital CMOS Logic Circuits

2007

ABSTRACT: Power and area are the two major concerns in design of any digital circuit. At present scenario low power device design and its implementation have got a significant role in the field of nano electronics. However much research not has been done at ultra-low power with acceptable performance and high performance design with power. To achieve the ultra-low power requirement is to operate the digital logic gates in subthreshold region. This paper investigates the analysis of CMOS technology in 45 nm channel length where the relative study of average power dissipation of CMOS inverter. We analyze and compare CMOS Inverter and other logic gates in subthreshold region. The subthreshold current is found to be exponentially related to the gate voltage. Thus,this exponential relationship not only gives an exponential reduction in power consumption, but also an exponential increase in delay. The simulation results are taken at 45nm using CMOS technology with the help of Cadence tool...