Analysis of Power, Performance and Area at sub-micron ASIC implementation (original) (raw)

This paper aims at understanding the existing deep sub-micron and sub-micron implementation of a digital design, analyzing it in terms of power, area and performance (timing) and to come up with solutions and strategies to optimize the design in terms of power, area and timing. An effort was made to comprehend the constraints, causes and the requirements that may result in the existing implementation of the design. Also, various experiments were carried out to enhance the design in various aspects like power, area and timing. Benefits of experiments and tradeoffs required were comparatively analyzed. An effort was made to experiment for optimum solutions and strategies to balance the requirements. The key areas stressed upon in this paper are the 28-nm technologies which pose some unique challenges, such as Low-Power Design, Restricted Design Rules, and Design for Yield. Several design examples have been presented, highlighting key techniques employed in the Synopsys® IC Compiler. K...