A 1.5 V 14 b 100 MS/s self-calibrated DAC (original) (raw)
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A 1.5-v 14-bit 100-MS/s self-calibrated DAC
IEEE Journal of Solid-State Circuits, 2003
Large-area current source arrays are widely used in current-steering digital-to-analog converters (DACs) to statistically maintain a required level of matching accuracy between the current sources. This not only results in large die size but also in significant degradation of dynamic range for high-frequency signals. To overcome technology barriers, relax requirements on the layout, and reduce DAC sensitivities to process, temperature, and aging, calibration is emerging as a viable solution for the next-generation high-performance DACs. In this paper, a new foreground calibration technique suitable for very-low-voltage environments is presented which effectively compensates for current source mismatch, and achieves high linearity with small die size and low power consumption. Settling and dynamic performance are also improved due to a dramatic reduction of parasitic effects. To demonstrate this technique, a 14-bit DAC prototype was implemented in a 0.13-m digital CMOS process. This is the first CMOS DAC reported that operates with a single 1.5-V power supply and achieves 14-bit linearity with less than 0.1 mm 2 of active area. At 100 MS/s, the spurious free dynamic range is 82 dB (62 dB) for signals of 0.9 MHz (42 MHz) and the power consumption is only 16.7 mW.
Dynamic calibration of current-steering DAC
High accuracy Digital to Analog Converters (DACs) exist for improving the output impedance of the current are becoming increasingly important as the common used source. For example, cascoded current sources and currentbuilding block in communication systems. With the increasing of steering switches can be used to increase the output the update rate, dynamic performance of such DACs at high impedance. frequencies is ofparticular interest. The dynamic performance is often characterized by the spurious free dynamic range (SFDR) Many calibration approaches [2], [5], [6] have been and the SFDR is limited by the spectral harmonics which are reported in the literatures for improving DAC performance attributed by system nonlinearities. In this paper, the dynamic focusing mainly on reducing the static nonlinearity. In higher nonlinearity is analyzed and its effect on the output waveform is frequency ranges, little has been presented to lower the discussed. A novel approach is presented to calibrate the dynamic dynamic nonlinearities [7]. Some modest improvements in errors. The validity ofthis approach is demonstrated with a 15-bit high frequency SFDR have been reported with return-to-zero current steering DAC. Simulation results show that the approach structures (RTZ) at the expense of sacrificing half of the is robust and the SFDR can be correspondingly significantly signal power. improved by using this calibration scheme.
A 15-bit binary-weighted current-steering DAC with ordered element matching
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Device variability has become one of the fundamental challenges to high-resolution and high-accuracy DACs in nanometer and emerging processes. This paper introduces a 15bit binary-weighted current-steering DAC in a standard 130nm CMOS technology, which utilizes a new random mismatch compensation theory called ordered element matching to improve the static linearity performance with the presence of large variability. The chip's core area is less than 0.42mm 2 , among which the 7-bit MSB current source area is well within 0.021mm 2 . Measurement results have shown that the DAC's DNL and INL can be reduced from 9.85LSB and 17.41LSB to 0.34LSB and 0.77LSB, respectively.
A 12-bit intrinsic accuracy high-speed CMOS DAC
IEEE Journal of Solid-State Circuits, 1998
A 12-bit intrinsic accuracy digital-to-analog (D/A) converter integrated in a standard digital 0.5 m CMOS technology is presented. It is based on a current steering doubly segmented 6 + 2 + 4 architecture and requires no calibration, no trimming, or dynamic averaging. The differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 and 0.6 least significant bits (LSB's), respectively. The measured glitch energy is 1.9 pV 1 1 1 s. For a 12-bit resolution, the converter reaches an update rate of 300 MS/s. By reducing the voltage supply of the latches to 2.0 V, the glitch energy is reduced to sub-pV 1 1 1 s, and the update rate reaches 500 MS/s, for a resolution of 8 bits. The worst case power consumption is 320 mW, and it operates from a single 3.3 V voltage supply. The die area is 3.2 mm 2 .
A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With $ > $70 dB SFDR up to 500 MHz
IEEE Journal of Solid-State Circuits, 2011
A current-steering digital-to-analog converter (DAC) was fabricated using a 90 nm CMOS technology. Its dynamic performance is enhanced by adopting a digital random return-to-zero (DRRZ) operation and a compact current cell design. The DRRZ also facilitates a current-cell background calibration technique that ensures the DAC static linearity. The measured differential nonlinearity (DNL) is 0.5 LSB and the integral nonlinearity (INL) is 1.2 LSB. At 1.25 GS/s sampling rate, the DAC achieves a spurious-free dynamic range (SFDR) better than 70 dB up to 500 MHz input frequency. The DAC occupies an active area of 1100 750 m 2. It consumes a total of 128 mW from a 1.2 V and a 2.5 V supply. Index Terms-Background calibration, current-steering, D/A converters, digital random return-to-zero (DRRZ), digital-analog conversion, digital-to-analog converter (DAC), return-to-zero (RZ).
A strategy for implementing dynamic element matching in current-steering DACs
2000
Interesting comparisons of dynamic element matching (DEM) techniques, have been presented during the last decade. However, not many chip implementations of these DEM techniques have been presented so far. A brief review of different DEM techniques are presented in this paper together with a strategy for implementing the partial randomization DEM, PRDEM, technique in a 3.3 V supply, 14 bit CMOS current-steering wideband digital-to-analog converter (DAC)
A 14-bit dual current-steering DAC
2004
ABSTRACT A 14-bit dual current-steering digital-to-analog converter implemented in a 0.25 µm CMOS process is presented in this work. Both implementation issues and measurement results are presented. The measured spurious-free dynamic range is higher than 73 dB for signal frequencies up to 3 MHz, and a measured multi-tone power ratio of approximately 71 dB is reported for an ADSL-like input.
10-Bit Current Steering DAC in CMOS 130nm Technology
This paper proposed a 10-bit current steering (segmented architecture)digital-to-analog converter, with different sizes of current sources. The proposed 10-bit digital-to-analog converter was implemented using TSMC CMOS 130 nm 1P2M technology. The power consumption was approximately 23.015 mW at the sample rate of 200 MHz, and the supply voltage was 3.3 V. It achieved a DNL (differential nonlinearity) and an INL (integral nonlinearity) of 0.06 LSB and 0.04 LSB, respectively. In segmented (4LSB-6MSB) architecture the measured SFDR (spurious free dynamic range) was 88.156 dB. This work presented a good performance compared with other researches in DNL, INL and area.
A Tri-level Current-Steering DAC Design with Improved Output-Impedance Related Dynamic Performance
2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)
This paper presents a design of a low-latency 12-bit linear tri-level current-steering digital-toanalogue-converter for use in continuous-time ADCs. The DAC design achieves 12-bit static linearity, while the combination of DAC slice impedance matching with a proposed compensation technique reduces outputimpedance related distortion. The technique demonstrates ~10dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/s. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology.
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