Novel On-Chip Circuit for Jitter Testing in High-Speed PLLs (original) (raw)

2005, IEEE Transactions on Instrumentation and Measurement

We propose a novel on-chip circuit to measure the jitter present at the output of phase-locked loops (PLLs) used for generating phase-synchronous, frequency-multiplied clocks. This measure is performed at every period of the PLL reference clock, and a digital output encoded by means of a thermometer code is obtained. Such a digital output is then analyzed in order to confirm on-chip whether or not the jitter is within specifications. Our proposed circuit is able to test PLLs providing an output frequency in the gigahertz range. Compared to alternate techniques, that proposed here requires lower costs in terms of area overhead (requiring an area 12% of the PLLs' area) and circuit complexity, while featuring higher or comparable accuracy and lower or comparable test time. Index Terms-Jitter, on-chip measurement, phase-locked loops (PLLs), testing. I. INTRODUCTION P HASE-LOCKED loops (PLLs) are basic component blocks of today's ICs [1]. They are widely used for clock multiplication in microprocessor and data communication circuits [2]. The deviation in frequency and phase of the signal generated at the output of the PLL is known as PLL jitter. It may be due to power supply noise, PLL dead zone region, internal and external crosstalk, and potential noise associated with all ICs [3]. The continuous increase in the operation frequency of modern microprocessors and communication systems is tightening PLLs' jitter requirements to a few tens of picoseconds in order to prevent jitter from becoming a high percentage of the cycle time. Jitter out of specification may cause data loss or computational errors, with dramatic consequences on system reliability. These stringent requirements on PLLs' jitter have increased the relevance of jitter measurement techniques. Traditionally, jitter measurement has been performed off-chip by spectrum analyzers, automatic test equipment (ATE), real-time sampling oscilloscopes, or jitter-dedicated instruments, like time-interval analyzers (TIAs) and counter-timers. Clearly, jitter measurement relies on the utilized external equipment. This traditional approach has become extremely expensive for today's high-speed ICs. Consequently, several alternative off-chip methods, as well as on-chip solutions, have been proposed in literature (e.g., those in [4]-[12]).