A New Noise Shaping Approach for Sigma-Delta Modulators Using Two-Stage Feed-Forward Delays and Hybrid MASH-EFM (original) (raw)
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A Non-Feedback -Σ Modulator for Digital-to-Analog Conversion Using Digital Frequency Modulation
Analog Integrated Circuits and Signal Processing, 2004
This paper describes a novel noise-shaping Δ-Σ modulator for D/A-conversion which has no global feedback. The proposed topology is well suited for a pipelined clocking scheme allowing increased oversampling ratios for both first and higher order modulators. The maximum clock-frequency of the new modulator is limited only by the delay through one single accumulator regardless of modulator order, which represents a huge saving compared to the conventional modulator. The converter is very modular and scales easily to higher modulator orders. Still the proposed topology is mathematically equivalent to the classical Δ-Σ modulator. Theoretical analysis and circuit simulations for a first- and second-order modulator are presented. The first-order circuit has been implemented in a FPGA-circuit from Altera and measured results are presented.
Preliminary Design and Comparative Analysis Between Different DT Sigma-Delta Modulators
Sigma-Delta analog-to-digital converters (ADCs) are known for providing high resolutions when compared to other ADC architectures. They are composed of a sigma-delta modulator and a digital decimation filter. This work focuses is in the high-level design of discrete-time sigma-delta modulators (DT-SDMs) whereas the design and implementation of first and second-order modulators are analyzed using Matlab. A complete performance analysis of each modulator is described using the cascade of integrators in feedback (CIFB) structure. It is worth mentioning that our study has a focus on medium bandwidth (BW) applications, as such audio applications. Besides, we target low-voltage operations. This work is at an early stage, thus only first and second-order modulators are investigated. This work considers a BW of 24 kHz, a sampling frequency of 6.144 MHz, and oversampling (OSR) of 128. Index Terms-sigma-delta modulators, sigma-delta ADC, DT-SDM CIFB structure.
Delta-sigma modulators using frequency-modulated intermediate values
IEEE Journal of Solid-State Circuits, 1997
This paper describes a new first-and second-order delta-sigma modulator concept where the first integrator is extracted and implemented by a frequency modulator with the modulating signal as the input. The result is a simple delta-sigma modulator with no need for digital-to-analog converters, allowing straightforward multi-bit quantization. Without the frequency modulator, the circuit becomes a frequency-to-digital converter with delta-sigma noise shaping. An experimental first-and second-order modulator have been implemented in a 1.2-¼m standard digital CMOS process and the results confirm the theory. For the first-order modulator an input signal amplitude of 150mV resulted in a SQNR of ³115dB at 2MHz sampling frequency and signal bandwidth 500Hz.
Sigma-Delta Modulator Design and Analysis for Audio Application
International Journal of Engineering Trends and Technology, 2015
A Sigma-delta modulator is designed in 180nm CMOS process for digital Audio applications. This design is simulated on S-Edit of Tanner EDA tool. In this design continuous time sigma-delta modulator is implemented to reduce the noise problem. This sigma-delta modulator also helps to reduce power consumption of circuit. In these design two stage op-amps is used to implement modulator. Also this design uses second order continuous time modulator for increasing SNR. Circuit design an 11bit low power sigma-delta modulator for digital audio application is given, using a single bit quantizer. The power supply for this circuit is only 1.8v; the modulator achieves 72dB SNR in a 20 KHz BW, while consuming 1mW.
Iscas, 2002
¦¡-modulation is a proven method to realize high-resolution A/D converters. A particularly efficient way to implement such a modulator uses double-sampling where the sampling frequency is twice the master-clock frequency. Unfortunately path mismatch between both sampling branches causes a part of the quantisation noise to fold from the Nyquist frequency back in the signal band. This degrades the performance. In this paper we show that multi-bit quantisation provides a partial solution for this problem.
Dual-clock MASH delta-sigma modulator employing a frequency modulated intermediate signal
IEICE Electronics Express, 2006
A dual-clock MASH (multi-stage noise shaping) deltasigma modulator (DSM) is proposed for high performance analog-digital converter. This employs a DSM using a frequency modulated intermediate signal (FMDSM) for the last stage. The sampling clock frequency for the last stage can be increased due to the features of the FMDSM. It is shown that this can increase the SNR beyond the conventional MASH DSMs.
On the Design of a 2-2-0 MASH Delta-Sigma-Pipeline Modulator
— In this paper, a 2-2-0 MASH delta-sigma modulator is presented. This architecture consists of two single-bit second-order delta-sigma modulators in the first and second stages and a pipeline ADC in the last stage. In the conventional cascaded delta-sigma-pipeline modulators, consisting of a single-loop delta-sigma modulator at the first stage and a pipeline ADC at the second stage, in order to achieve higher order noise shaping and stability of the modulator simultaneously, multi-bit quantizer and multi-bit DAC must be used, which cause the DAC non-linearity problem. Implementation of the cascaded delta-sigma-pipeline structure on a single bit 2-2 MASH delta-sigma modulator is proposed in this work and its advantages and disadvantages are considered in detail. The key feature of the proposed modulator is taking the advantages of 2-2 MASH delta-sigma modulator compared to other conventional cascaded delta-sigma-pipeline modulators. This architecture offers the possibility of implementation of a power efficient, fourth-order cascaded delta-sigma-pipeline modulator without having the stability or DAC non-linearity problems. The mismatch between the digital and analog filters in the pipeline part is also shaped by the order of two and therefore its hazardous effects are reduced. The system level simulation using MATLAB/SIMULINK confirms the usefulness of the presented structure.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017
A 4-bit, third-order, continuous-time modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented in detail. This enables easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high linearity while simplifying the DAC design, circuit-and layout-level design techniques for minimizing switching time mismatches among and inside the DAC unit elements are presented. As a result, glitch-induced harmonic distortion is greatly reduced, requiring only a simple dataweighted averaging for the multibit DAC. In combination with multipath multistage op amps used to implement active-RC integrators, the presented techniques make it feasible to design a high-performance modulator with low power and small area, which is desired in many wireless communications systems. The experimental prototype, implemented in a 28-nm CMOS technology, achieves a 72.6-dB dynamic range, a 70.7-dB peak SNR, and a 70.1-dB peak signal-to-noise plus distortion ratio for a signal bandwidth of 20 MHz. The total power consumption is 6 mW from a 1-and 1.4-V supply, of which analog and digital circuits dissipate 4.5 and 1.5 mW, respectively. The total active area is 0.058 mm 2 .
Frequency Domain Min-Max Optimization of Noise-Shaping Delta-Sigma Modulators
IEEE Transactions on Signal Processing, 2000
This paper proposes a min-max design of noiseshaping delta-sigma (∆Σ) modulators. We first characterize the all stabilizing loop-filters for a linearized modulator model. By this characterization, we formulate the design problem of lowpass, bandpass, and multi-band modulators as minimization of the maximum magnitude of the noise transfer function (NTF) in fixed frequency band(s). We show that this optimization minimizes the worst-case reconstruction error, and hence improves the SNR (signal-to-noise ratio) of the modulator. The optimization is reduced to an optimization with a linear matrix inequality (LMI) via the generalized KYP (Kalman-Yakubovich-Popov) lemma. The obtained NTF is an FIR (finite-impulse-response) filter, which is favorable in view of implementation. We also derive a stability condition for the nonlinear model of ∆Σ modulators with general quantizers including uniform ones. This condition is described as an H ∞ norm condition, which is reduced to an LMI via the KYP lemma. Design examples show advantages of our design.