Power Virus Generation Using Behavioral Models of Circuits (original) (raw)

Characterization-free behavioral power modeling

… on Design, automation and test in …, 1998

We propose a new approach to RT-level power modeling for combinational macros, that does not require simulationbased characterization. A p attern-dependent power model for a macro is analytically constructed using only structural information about its gate-level implementation. The approach has three main advantages over traditional techniques: i it provides models whose accuracy does not depend on input statistics, ii it o ers a wide range of tradeo between accuracy and complexity, and iii it enables the construction of pattern-dependent conservative upper bounds.

Analytical model for high level power modeling of combinational and sequential circuits

Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design, 1999

In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a (combinational or sequential) logic circuit on its input/output signal switching statistics. The resulting power macromodel, consists of a quadratic or cubic equation in four variables, that can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gate-level) description of the circuit, we describe a characterization process that uses a recursive least squares (RLS) algorithm by which such a equation-based model can be automatically built. The four variables of our model are the average input signal probability, average input switching activity, average input spatial correlation coefficient and average output zero-delay switching activity. This approach has been implemented and models have been built and tested for many combinational and sequential benchmark circuits. by the Semiconductor Research Corporation (SRC 97-DJ-484), with technical mentorship from Texas Instruments Inc.

K2: An estimator for peak sustainable power of VLSI circuits

1997

Abstract New measures of peak power in the context of sequential circuits are proposed. This paper presents an automatic procedure to obtain very good lower bounds on these measures as well as the actual input vectors that attain such bounds. The initial state of the circuit is an important factor in determining the amount of switching activity in sequential circuits and is taken into account. A peak power estimator tool K2 was developed using genetic techniques.

Instruction level power model of microcontrollers

1999

In the design of low power systems, it is important to analyze and optimize both the hardware and the software component of the system. To evaluate the software component of the system, a good instruction-level energy model is essential. In this paper we present a methodology for instruction level modelling of microcontrollers using gate level power estimation tools. We use the microcontroller, M68HC11, to illustrate this method. We study two different implementations of the microcontroller and show that the energy consumption of each instruction is quite different. Our study reveals that data correlation does not significantly affect the energy consumption of most instructions. Finally, we show the correctness of this model by running some sample programs and showing that the predicted energy estimates are quite close to the actual estimates.

Static power modeling of 32-bit microprocessors

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002

The paper presents a novel strategy aimed at modelling instruction energy consumption of 32-bits microprocessors. Differently from former approaches, the proposed instruction-level power model is founded on a functional decomposition of the activities accomplished by a generic microprocessor. The proposed model has significant generalization capabilities. It allows estimation of the power figures of the entire instruction-set starting from the analysis of a subset, as well as to power characterize new processors by using the model obtained by considering other microprocessors. The model is formally presented and justified and its actual application over five commercial microprocessors is included.This static characterization is the basic information for system-level power modelling of hardware/software architectures.

A high-level microprocessor power modeling technique based on event signatures

Journal of Signal Processing Systems, 2010

This paper presents a technique for high-level power estimation of microprocessors. The technique, which is based on abstract execution profiles called 'event signatures', operates at a higher level of abstraction than commonly-used instruction-set simulator (ISS) based power estimation methods and should thus be capable of achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early system-level design space exploration. In this paper, we also compare our power estimation results to those from the instruction-level simulators Wattch and Sim-Panalyzer. In these experiments, we demonstrate that with a good underlying power model, the signature-based power modeling technique can yield accurate estimations (a mean error of 3.1% compared to Wattch in our experiments). At the same time, our signature-based power modeling technique is at least an order of magnitude faster than the simulations performed by Wattch or Sim-Panalyzer.

Reducing the complexity of instruction-level power models for VLIW processors

Design Automation for Embedded Systems, 2005

Aim of this paper is to propose a high-level power exploration framework based on an instruction-level energy model for VLIW (Very Long Instruction Word) architectures. More specifically, the present paper deals with the reduction of the complexity of the energy model of K -issue VLIW processors from exponential with respect to the number of operations within the Instruction Set O(|I S A| K ) to quadratic (O(K * |I S A| 2 )). The complexity of the energy model has been further simplified by automatically clustering the operations in the ISA with respect to their average energy. Globally, the proposed approach reduces the complexity of the characterization problem for a K -issue VLIW processor to quadratic (O(K * |C| 2 )) with respect to the number of operation clusters. In this way, a more efficient characterization of the VLIW core power consumption can been achieved, while preserving the accuracy of the power estimates. The proposed model has been further extended to provide early power figures and energy/performance trade-offs for multi-cluster VLIW architectures composed of multiple data-path units and a single instruction cache control unit. The proposed high-level power estimation methodology has been applied to the Lx 4-issue VLIW pipelined processor provided by STMicroelectronics.

Power Macromodeling For High Level Power Estimation

Proceedings of the 34th Design Automation Conference, 1997

A modeling approach is presented that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching activity. The resulting power macromodel, consisting of a single three dimensional table, can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gatelevel) description of the circuit, we describe a characterization process by which such a table model can be automatically built. In contrast to other proposed techniques, this can be done for any given logic circuit without any user intervention, and applies to all possible input/output signal statistics; it does not require one to construct specialized analytical equations for the power dissipation. The three dimensions of our table-based model are the average input signal probability, average input transition density, and average output zero-delay transition density. This approach has been implemented and models have been built for many benchmark circuits. Over a wide range of input signal statistics, we show that this model gives very good accuracy, with an RMS error of under about 6%.

Power modeling for high-level power estimation

Very Large Scale Integration (VLSI) …, 2000

In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching statistics. The resulting power macromodel, consisting of a single four-dimensional table, can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gate-level) description of the circuit, we describe a characterization process by which such a table model can be automatically built. The four dimensions of our table-based model are the average input signal probability, average input transition density, average spatial correlation coefficient and average output zero-delay transition density. This approach has been implemented and models have been built for many benchmark circuits. Over a wide range of input signal statistics, we show that this model gives very good accuracy, with an RMS error of about 4% and average error of about 6%. Except for one out of about 10,000 cases, the largest error observed was under 20%. If one ignores the glitching activity, then the RMS error becomes under 1%, the average error becomes under 5% and the largest error observed in all cases is under 18%.

Current dynamics-based macro-model for power simulation in a complex VLIW DSP processor

IEE Proceedings - Computers and Digital Techniques

A methodology and a macro-modelling approach are presented for analysing low-level current dynamics at the instruction and program level for a complex VLIW DSP processor core. An instruction-level macro-model, whose input parameters can be extracted from the DSP core's assembly level program, is introduced for power modelling. For the first time, dynamic power models of algorithms are introduced and verified with real power measurements of a DSP processor core in a VLSI chip. Results from both cryptographic and bubble sort applications show that dynamic power can be modelled with an average error in energy estimation ranging from 0.3% to 9.7%. The instruction-level macro-model of power also supports different clock frequencies and compressed algorithmic traces, important for security aware compilers. In general, the research is important for analysing and modelling the impact of software on power, the design of embedded cryptographic VLSI systems that are safe from power attacks, and for reliable design by detecting the peak current values generated by the software application.