Multiple Si layer ICs: motivation, performance analysis, and design implications (original) (raw)
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IEEE Transactions on Advanced Packaging, 2005
A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a physical packing density many times greater than today's advanced multichip modules. This technology overcomes the resistance–capacitance (RC) delays associated with long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and provides a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and three dimensional (3-D) stacking technology have the potential to reduce significantly the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally. Although TSVs have great potential, there are many fabrication obstacles that must be overcome. This paper discusses the architectural possibilities enabled by TSVs, and the necessary TSV dimensions for dense$Z$-axis interconnect among logic blocks. It then describes the TSV requirements for the Defense Advanced Research Projects Agency (DARPA)-funded Vertically Integrated Sensor Arrays (VISA) program, and how those requirements differ from a more general purpose TSV technology. Finally, the TSV fabrication process being implemented at the University of Arkansas (UA) is described in detail. Though this process is being developed for the VISA program, it embodies many of the characteristics of a widely applicable TSV technology.
2014
Semiconductor technology continues its progress in the field of 3DICs. Using stack structures through silicon via (TSV), the concept of 3D IC deals with introducing another dimension in recent designs. In fact, 3D ICs accompanying with TSV cells replace the existent connections in 2D ICs. Optimizing 3D ICs; however, is still in its early stages in many aspects. There are still some problems in locating standard and TSV cells regarding time optimization. In the present study, after queuing the layer and based on its segmentation, first we proposed a methodology for locating cells. Then, we dealt with simultaneous addressing of the pressure caused by the queuing process. Simulated fusion was applied to optimize timing and reduce wire length. Finally, an appropriate method is used to prove the procedures so that it can omit the overlaps between the cells and also the TSV cells. The results of the conducted experiments showed that both wavelength and delay in critical routes are more im...
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