Parity Based Fault Detection Techniques for S-Box/ Inv S-Box Advanced Encryption System (original) (raw)
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Fault detection schemes for the Advanced Encryption Standard are aimed at detecting the internal and malicious faults in its hardware implementations. In this paper, we present fault detection structures of the S-boxes and the inverse S-boxes for designing high performance architectures of the Advanced Encryption Standard. We avoid utilizing the look-up tables for implementing the S-boxes and the inverse S-boxes and their parity predictions. Instead, logic gate implementations based on composite fields are used. We modify these structures and suggest new fault detection schemes for the S-boxes and the inverse S-boxes. Using the closed formulations for the predicted parity bits, the proposed fault detection structures of the S-boxes and the inverse S-boxes are simulated and it is shown that the proposed schemes detect all single faults and almost all random multiple faults. We have also synthesized the modified S-boxes, inverse S-boxes, mixed S-box/inverse S-box structures, and the whole AES encryption using the 0.18μ CMOS technology and have obtained the area, delay, and power consumption overheads for their fault detection schemes. Furthermore, the fault coverage and the overheads in terms of the space complexity and time delay are compared to those of the previously reported ones.
Fault Detection Technique for Compact AES Design
Cryptography is a method that has been developed to ensure the secrecy of messages and transfer data securely. Advanced Encryption Standard (AES) has been made as the first choice for many critical applications because of the high level of security and the fast hardware and software implementations, many of which are power and resource constrained and requires reliable and efficient hardware implementations. Naturally occurring and maliciously injected faults reduce the reliability of Advanced Encryption Standard (AES) and may leak confidential information. In this paper, a lightweight concurrent fault detection scheme for the AES is presented. In the proposed approach, the composite field S-box and inverse S-box are divided into blocks and the predicted parities of these blocks are obtained. For high speed applications, S-box implementation based on lookup tables is avoided. Instead, logic gate implementations based on composite fields are utilized. A compact architecture for the AES Mix-columns operation and its inverse is also presented. This parity-based fault detection scheme reaches the maximum fault coverage when compared to other methods of fault detection. The proposed fault detection technique for AES encryption and decryption has the least area and power consumption compared to their counterparts with similar fault detection capabilities.
Advanced Fault Detection Scheme for AES Architecture
Cryptography is a method that has been developed to ensure the secrecy of messages and transfer data securely. The Advanced Encryption Standard (AES) is the newly accepted symmetric cryptography standard for transferring block of data securely. However, the natural and malicious injected faults reduce its reliability and may cause confidential information leakage. The objective of this paper is to find optimized fault detection schemes for reaching reasonable fault coverage in the high performance AES implementations. In order to provide low cost complexity signature, two sets of error indication flag is used. Thisstructure can be applied to both look-up tables and logic gate for the implementation of S-box and inverse S-box and their parity predictions. Defects in the logic gates causedeither by the natural faults or malicious injected faults that are detected independent of the method the S-box is implemented Moreover, the overhead costs, including space complexity and time delay of the proposed schemes are analyzed. Finally, our simulation results show the error coverage of greater than 99 percent for the proposed schemes. Index Terms-Advanced Encryption Standard, S-Box, inverse S-box, composite field, fault detection.
Least Complex S-Box and Its Fault Detection for Robust Advanced Encryption Standard Algorithm
Advanced Encryption Standard (AES) is the symmetric key standard for encryption and decryption. In this work, a 128-bit AES encryption and decryption using Rijndael Algorithm is designed and synthesized using verilog code. The fault detection scheme for their hardware implementation plays an important role in making the AES robust to the internal and malicious faults. In the proposed AES, a composite field S-Box and inverse S-Box is implemented using logic gates and divided them into five blocks. Any natural or malicious faults which defect the logic gates are detected using parity based fault detection scheme. For increasing the fault exposure, the predicted parities of each of the block S-box and inverse S-box are obtained. The multi-bit parity prediction approach has low cost and high error coverage than the approaches using single bit parities. The Field Programmable Gate Array (FPGA) implementation of the fault detection structure has better hardware and time complexities.
A parity code based fault detection for an implementation of the Advanced Encryption Standard
17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings., 2002
Concurrent fault detection for a hardware implementation of the Advanced Encryption Standard (AES) is important not only to protect the encryption/decryption process from random faults. It will also protect the encryption/decryption circuitry from an attacker who may maliciously inject faults in order to find the encryption secret key. In this paper we present a novel fault detection scheme which is based on a multiple parity bit code and show that the proposed scheme leads to very efficient and high coverage fault detection. We then estimate the associated hardware costs and detection latencies.
The high level of security and the fast hardware and software implementations of the Advanced Encryption Standard have made it the first choice for many critical applications. Nevertheless, the transient and permanent internal faults or malicious faults aiming at revealing the secret key may reduce its reliability. In this paper, we present a concurrent fault detection scheme for the S-box and the inverse S-box as the only two nonlinear operations within the Advanced Encryption Standard. The proposed parity-based fault detection approach is based on the low-cost composite field implementations of the S-box and the inverse S-box. We divide the structures of these operations into three blocks and find the predicted parities of these blocks. Our simulations show that except for the redundant units approach which has the hardware and time overheads of close to 100 percent, the fault detection capabilities of the proposed scheme for the burst and random multiple faults are higher than the previously reported ones. Finally, through ASIC implementations, it is shown that for the maximum target frequency, the proposed fault detection S-box and inverse S-box in this paper have the least areas, critical path delays, and power consumptions compared to their counterparts with similar fault detection capabilities.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011
The faults that accidently or maliciously occur in the hardware implementations of the Advanced Encryption Standard (AES) may cause erroneous encrypted/decrypted output. The use of appropriate fault detection schemes for the AES makes it robust to internal defects and fault attacks. In this paper, we present a lightweight concurrent fault detection scheme for the AES. In the proposed approach, the composite field S-box and inverse S-box are divided into blocks and the predicted parities of these blocks are obtained. Through exhaustive searches among all available composite fields, we have found the optimum solutions for the least overhead parity-based fault detection structures. Moreover, through our error injection simulations for one S-box (respectively inverse S-box), we show that the total error coverage of almost 100% for 16 S-boxes (respectively inverse S-boxes) can be achieved. Finally, it is shown that both the application-specific integrated circuit and field-programmable gate-array implementations of the fault detection structures using the obtained optimum composite fields, have better hardware and time complexities compared to their counterparts.
the faults that accidently or maliciously occur in the hardware implementations of the Advanced Encryption Standard (AES) may cause erroneous encrypted/decrypted output. The use of appropriate fault detection schemes for the AES makes it robust to internal defects and fault attacks. In this paper, we present a lightweight concurrent fault detection scheme for the AES. In the proposed approach, the composite field S-box and inverse S-box are divided into blocks and the predicted parities of these blocks are obtained. Through exhaustive searches among all available composite fields, we have found the optimum solutions for the least overhead parity-based fault detection structures. Moreover, through our error injection simulations for one S-box(respectively inverse S-box), we show that the total error coverage of almost 100% for 16 S-boxes (respectively inverse S-boxes) can be achieved. Finally, it is shown that both the applicationspecific integrated circuit and field-programmable gate-array implementations of the fault detection structures using the obtained optimum composite fields, have better hardware and time complexities compared to their counterparts.
A Novel Parity Bit Scheme for SBox in AES Circuits
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, 2007
This paper addresses an efficient concurrent fault detection scheme for the SBox hardware implementation of the AES algorithm. Concurrent fault detection is important not only to protect the encryption/decryption process from random and production faults. It will also protect the system against sidechannel attacks, in particular fault-based attacks, i.e. the injection of faults in order to retrieve the secret key. We will prove that our solution is very effective while keeping the area overhead very low.
An efficient hardware-based fault diagnosis scheme for AES: performances and cost
… and Fault Tolerance in …, 2004
Since standardization in 2001, the Advanced Encryption Standard has been the subject of many research efforts, aimed at developing efficient hardware implementations with reduced area and latency. So far, reliability has not been considered a primary objective. Recently, several error detecting schemes have been proposed in order to provide some defense against hardware faults in AES. The benefits of such schemes are twofold: avoiding wrong outputs when benign hardware faults occur, and preventing the collection of information about the secret key through malicious injection of faults. In this paper, we present a complete scheme for parity-based fault detection in a hardware implementation of the Advanced Encryption Standard which includes a key schedule unit. We also provide a preliminary evaluation of the hardware and latency overhead of the proposed scheme.