Clock synchronization Research Papers - Academia.edu (original) (raw)

2025, Article

Chronobiotics represent a pharmacologically diverse group of substances, encompassing both experimental compounds and those utilized in clinical practice, which possess the capacity to modulate the parameters of circadian rhythms. These substances influence fluctuations in various physiological and biochemical processes, including the expression of core "clock" genes in model organisms and cell cultures, as well as the expression of clockcontrolled genes. Despite their chemical heterogeneity, chronobiotics share the common ability to alter circadian dynamics. The concept of chronobiotic drugs has been recognized for over five decades, dating back to the discovery and detailed clinical characterization of the hormone melatonin. However, the field remains fragmented, lacking a unified classification system for these pharmacological agents. The current categorizations include natural chrononutrients, synthetic targeted circadian rhythm modulators, hypnotics, and chronobiotic hormones, yet no comprehensive repository of knowledge on chronobiotics exists. Addressing this gap, the development of the world's first curated and continuously updated database of chronobiotic drugs-circadian rhythm modulators-accessible via the global Internet, represents a critical and timely objective for the fields of chronobiology, chronomedicine, and pharmacoinformatics/bioinformatics. The primary objective of this study is to construct a relational database, ChronobioticsDB, utilizing the Django framework and PostGreSQL as the database management system. The database will be accessible through a dedicated web interface and will be filled in with data on chronobiotics extracted and manually annotated from PubMed, Google Scholar, Scopus, and Web of Science articles. Each entry in the database will comprise a detailed compound card, featuring links to primary data sources, a molecular structure image, the compound's chemical formula in machine-readable SMILES format, and its name according to IUPAC nomenclature. To enhance the depth and accuracy of the information, the database will be synchronized with external repositories such as ChemSpider, DrugBank, Chembl, ChEBI, Engage, UniProt, and PubChem. This integration will ensure the inclusion of up-to-date and comprehensive data on each chronobiotic. Furthermore, the biological and pharmacological relevance of the database will be augmented through synchronization with additional resources, including the FDA. In cases of overlapping data, compound cards will highlight the unique properties of each chronobiotic, thereby providing a robust and multifaceted resource for researchers and practitioners in the field.

2025

We conduct a statistical study of human mobility using over 1000 hours of GPS traces of human walks involving 44 participants in five different locations, two university campuses, state fair, New York City, and Disney World. Our data reveals statistical features similar to those in what physicists have long called Levy random walks (or Levy walks). These features include heavy-tail distributions of flight lengths and super-diffusive nature of mobility. We find that these tendencies are likely caused by human intentions in deciding travel destinations (and distance and sojourn time thereof), but not by geographical constraints such as roads, buildings, boundaries, etc, and that geographical constraints, instead, cause truncations of flight lengths and discontinuity in the statistical tendency of mobility statistics. Based on these findings, we construct a simple Levy walk mobility model that emulates human walk patterns expected in outdoor mobile networks carried by humans. Based on these findings, we construct a simple Levy walk mobility model that emulates human walk patterns expected in outdoor mobile network environments. We demonstrate that the Levy walk model can be used to recreate the statistical patterns commonly observed in previous mobility studies such as the power-law distributions of human inter-contact times and that the simulation performance of mobile network routing protocols under the Levy walk model exhibits distinctive performance features unexplored under existing mobility models.

2025

In metropolitan areas the deployment of optical fiber and Gigabit Ethernets leads to an expansion of packetswitched networks with large available capacities. These capacities could thus be employed to carry traffic from existing GSM/UMTS base stations and PBX (Private Branch Exchanges). Carrying this traffic requires an emulation of E1/T1 telephone circuits over Ethernets, i.e. E1/T1 PDH/SDH signals from base stations need to be packetized and encapsulated in a circuit emulation adapter (CEA) before being sent over the Ethernet. The key problem with this emulation is to adjust the buffer play-out rate in the receiving CEA to the rate of the sending CEA. This synchronization is necessary: (i) to avoid long-time receiver buffer under-or overflows since base stations are up for weeks and months and (ii) to preserve the frequency of PDH signals across the Ethernet. TIK/ETH and Siemens have started the CoP (Circuit-over-Packets) project to address this problem and to build a new CEA demonstrator. This thesis documents laboratory measurements of the synchronization between pairs of CEA demonstrators over metropolitan Gigabit Ethernets, i.e. we have measured the Maximum Relative Time Interval Error (MRTIE) between the PDH signal that goes into the sending CEA and the PDH signal that comes out of the receiving CEA. To make measurements reproducible, we have employed the network emulator RplTrc [2] to emulate traffic patterns of a Gigabit Ethernets. RplTrc has also been developed by TIK/ETH. To get a feel for the achievements of the CoP project, we have additionally compared measurements of the CoP's CEA to measurements with three commercially available CEAs ("product A, B, C"). From our measurements, we conclude that the CoP's CEA generally outperforms the CEA C. The CoP's CEA also shows better performance in long-term synchronization stability than the CEA B. However, the synchronization algorithm of the CEA B is more robust to variable network conditions. Finally, we have found that the CEA A shows higher quality level for short-term synchronization stability than the CoP's CEA, while long-term behaviors are comparable. The CEA A is slightly more robust to different traffic scenarios, but equally sensitive to the limited delay (im)precision of RplTrc [2]. We explain this slightly better performance of the CEA A with the arithmetic limitations of the Siemens board used to implement the CoP's CEA demonstrator.

2025, Lecture Notes in Computer Science

The purpose of partial-order reduction techniques is to avoid exploring several interleavings of independent transitions when model checking the temporal properties of a concurrent system. The purpose of symbolic verification techniques is to perform basic manipulations on sets of states rather than on individual states. We present a general method for applying partial order reductions to improve symbolic verification. The method is equally applicable to the verification of finite-state and infinite-state systems. It considers methods that check safety properties, either by forward reachability analysis or by backward reachability analysis. We base the method on the concept of commutativity (in one direction) between predicate transformers. Since the commutativity relation is not necessarily symmetric, this generalizes those existing approaches to partial order verification which are based on a symmetric dependency relation. We show how our method can be applied to several models of infinitestate systems: systems communicating over unbounded lossy FIFO channels, and unsafe (infinite-state) Petri Nets. We show by a simple example how partial order reduction can significantly speed up symbolic backward analysis of Petri Nets.

2025, OCEANS 2009

Research into underwater acoustic communication has focused on time division multiple access (TDMA) communication protocols. Within a front-seat/backseat control architecture, effective communication is not guaranteed due to the strict clock synchronization requirement of the TDMA protocols. In the event of dropped messages during the cycle, the strict clock requirement can lead to message overlap and communication failure. In this paper, a novel, token-based medium access control (TMAC) solution for underwater acoustic broadcast is introduced. This solution is unique in the sense that it does not require that a ring be maintained for passing the token. TMAC provides a solution to the synchronization problem, ensuring effective communication within a front-seat/backseat control architecture. We expand on the structure and operation of the TMAC solution in the presence and absence of dropped messages. The solution is then applied to a mine countermeasure reference mission, and the re...

2025

Clock synchronization is crucial to a wireless sensor network but often difficult to maintain. In this paper, we propose a joint estimation method to estimate both target states and clock synchronization status based on sensor observations from an unsynchronized wireless sensor network. We build a multi-sensor state-space model to connect clock synchronization status with sequential state transition. We use the expectation-maximization algorithm, together with Monte Carlo approximations, for joint estimation. Numerical examples show that the proposed method converges to the true synchronization status and improves the accuracy of sequential state estimation by considering the synchronization status.

2025, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems

Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an asynchronous interconnect. Such a scheme can be used for point-to-point communication in a globally asynchronous locally synchronous (GALS) system, a possible methodology for managing the predicted increase in clock domains. We present interface wrapper circuits which permit communication between a locally synchronous producer and a locally synchronous consumer via an asynchronous interconnect. Such interfaces can also be used to mix asynchronous and synchronous modules. Clock pausing is used to guarantee that metastability will never result in failure. Arbitration between channel communication and the local clock is performed concurrently so that metastability resolution will rarely delay the clock. Simulation results show that the maximum performance of one data item per consumer clock cycle is achieved when the producer:consumer clock ratio is equal or greater to one. This communication mechanism is suited to other asynchronous interconnect methods which offer low power and high performance.

2025, IEEE Transactions on Instrumentation and Measurement

Industrial networks for distributed monitoring, control, and automation purposes require high-accuracy clock synchronization in topologies including long chains of cascaded nodes. Unfortunately, accuracy typically degrades as the number of devices and the distance from the synchronization reference node (i.e., the master or grandmaster) grows, because of the accumulation of multiple uncertainty contributions. To mitigate this problem, the so-called transparent clocks are used in some synchronization protocols, such as the precision transparent clock protocol used in PROFINET IO isochronous real time networks and the precision time protocol version 2, standardized as IEEE 1588-2008. In this paper, an optimal servo-clock in the mean square sense is proposed. The controller relies on both a Kalman filter that estimates the clock state difference with respect to the master and a static-state feedback assuring mean square stability even under the effect of significant fluctuations of the synchronization period. Several multiparametric simulation results in a case study based on the features of PROFINET IO devices confirm that excellent performance can be achieved with the proposed approach.

2025

Managing Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) issues is critical for ensuring the reliability and performance of high-speed interfaces in modern digital systems. As the complexity of integrated circuits and the demand for high-speed data transfer increase, the likelihood of encountering CDC and RDC challenges also rises, potentially leading to data corruption, timing violations, and system failures. This study explores the intricate nature of CDC and RDC, providing a comprehensive overview of their definitions, types, and common issues associated with each.

2025, Ubiquitous Computing Systems

Wireless Sensor Networks, aiming to monitor the real world's phenomena reliably, need to combine and postprocess the detected individual events. This is not possible without reliable information of the context of the individual event. One such information of very high importance is time. It enables ordering of events as well as deduction of further data like rates and durations. An unreliable time base influences not only the ordering of events, but also the deduced values, which in consequence are unreliable as well. Therefore the synchronization of the clocks of the individual nodes is of high importance to the reliability of the system. On the other hand tight and reliable synchronization typically induces a large message overhead, which is often not tolerable in WSN scenarios. This paper proposes a new hybrid synchronization mechanism enabling tight synchronization in single hop environments and looser synchronization in multi hop environments. The lack of a guaranteed synchronization precision is mitigated by an explicit synchronization uncertainty, which is passed to the application. This enables the application to react to changes in the current synchronization precision.

2025

The actual trend towards more driver assisting systems in automotive scenarios induces a need for additional sensory data from the environment. Those perceptions can be generated by the inherent sensor systems or by external transducers. However, these data may be affected by faults and uncertainties, which may not be obvious to other cars receiving the data. Additionally, the management and dissemination of the data between the plethora of cars on the road is a big challenge. Therefore, this paper proposes an extension to existing complex event detection systems to support fault and uncertainty aware collaborative applications. An automotive scenario was chosen to illustrate the new approach. Consequently, the requirements of automotive scenarios were described and existing complex event systems were evaluated against these requirements. The extended system is called a complex event processing system, since it tries to enable sensor processing in an highly dynamic event system. To reach this goal additional attributes are introduced to the basic event schemes. Finally the processing steps are adopted to cope with the new quality attributes validity and uncertainty.

2025, Lecture Notes in Computer Science

Core operations (e.g. TDMA scheduler, synchronized sleep period, data aggregation) of many proposed protocols for different layer of sensor network necessitate clock synchronization. Our paper mingles the scheme of dynamic clustering and diffusion based asynchronous averaging algorithm for clock synchronization in sensor network. Our proposed algorithm takes the advantage of dynamic clustering and then applies asynchronous averaging algorithm for synchronization to reduce number of rounds and operations required for converging time which in turn save energy significantly than energy required in diffusion based asynchronous averaging algorithm.

2025, IEEE Transactions on Instrumentation and Measurement

This paper presents a strict timing-coherent digital signal processing architecture. The main requirement is that programmable events can be produced within predictable time intervals with tight accuracy (timing errors < 1 ns). This characteristic is essential to ultrasound beamforming. The followed approach defines a modular and scalable architecture (AMPLIA), which is configured as a multibranch pipeline. This arrangement guarantees timing coherence along all the system, independent of the number of processing modules. An important element of the architecture is the interface and control unit (ICU), which decouples the asynchronous communication channel with a host computer to the strictly timing-coherent domain of the signal processing system. Furthermore, in the beamforming application, several elements have a great impact on system timing resolution, particularly when dynamic focusing is involved. This paper addresses the issues of coded excitation, analog-to-digital (A/D) conversion, and signal interpolation in achieving dynamic focusing by progressive focusing correction with processing rates of several gigasamples per second and tight timing accuracy.

2025, arXiv (Cornell University)

In this paper I give a major update of quantum gravity framework project. The heuristic conceptual framework proposed in previous versions is expanded to include structure formation and consciousness in the universe. A Path Integral version of decoherence in curved space-time is introduced as major update. Then we discuss the philosophical insights into structure formation in the universe and consciousness. We introduce various mathematical concepts to describe structure formation in the universe and consciousness. 1 Originally published on June 24 2021 as the 4.0 version. In this version 4.1, updated on August 27 2023, references are added, proofreading was done and a few modifications are made in various sections and explained there. An important update in 4.1 is in section 3.3, in the end, where trace-free extrinsic curvature is introduced to detect the rest frame foliation. For the latest updates proper discussions, comments, and issues, please visit www.qstaf.com. Much of the discussions, updates, and supplementary downloadable materials regarding this project will be mostly available on www.qstaf.com, and other websites referred to such as the researchgate. Update information will be provided on social media (www.qstaf.com/links).

2025

Clock synchronization is a crucial issue in the operation of wireless sensor networks. Although the existing synchronization algorithms under linear clock model assumptions perform well for short periods, they will become problematic for applications with long-term requirements. In this paper, we consider a more realistic and flexible relationship model for two clocks and exploit a Taylor expansion to approximate the relationship. Based on this model and a two-way time message exchange procedure, an estimation algorithm is proposed to recover the relationship and then achieve the synchronization. Finally, simulation results demonstrate that the proposed algorithm improves the accuracy of synchronization as compared to existing algorithms in many scenarios, and is also robust to different distributions of random delays.

2025

This paper investigates the problem of clock synchronization of nodes in a wireless sensor network based on the two-way timing message exchange mechanism with an unknown deterministic transmission delay and random exponential transmission delays. Without knowing the fixed delay, a novel synchronization scheme is proposed for the linear clock model, which works well in both symmetric and asymmetric links. In the proposed algorithm, the clock skew and offset are estimated by directly utilizing mean square error as the metric to be optimized. This consideration results in significant performance improvements compared to the existing synchronization methods, especially for a small number of observations and large standard deviation of the random delays.

2025

This paper investigates the clock synchronization problem for Device-to-Device (D2D) communication without infrastructure. Employing affine models for local clocks, it is proposed a random broadcast based distributed consensus clock synchronization algorithm. In the absence of transmission delays, we theoretically prove the convergence of the proposed scheme, which is further illustrated by the numerical evaluations. On the other hand, when the delays are also taken into account, the proposed approach still performs well. Besides, it is further concluded from the simulations that the proposed scheme is robust against dynamic topologies and scalable to the increased number of devices, and has a fast speed regarding the synchronization error decrease.

2025, Proceedings of the IEEE

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALSVone based on synchronizer, the other on stoppable clockVare described and analyzed.

2025, Light-Driven Clocking Mechanism Using GaN LEDs and FinFET Transistors

This paper proposes a novel, energy-efficient approach to clock signal generation in classical computing systems. We replace traditional electrical oscillator-based clock generators with a photonic clocking mechanism using Gallium Nitride (GaN) Light-Emitting Diodes (LEDs) and Fin Field-Effect Transistors (FinFETs). The goal is to evaluate the feasibility and performance of using controlled light pulses to flip light-sensitive FinFETs, thereby simulating clock cycles and reducing energy consumption and thermal output. The proposed architecture enables clock frequencies in the 10-100 GHz range and demonstrates improved energy efficiency and heat dissipation compared to traditional CMOS oscillator-based clocking methods.

2025

In this paper, secure based novel clock synchronization in wireless sensor network for event driven measurement application is proposed with security. The main objectives are 1) To provide high accuracy in the area where an event is detected 2) To ensure long network lifetime 3) To ensure security based packet transmission. The complexity of a problem arises from first two properties that usually in clash. To increase the synchronization accuracy, the nodes are required to transfer synchronization packets at higher rate thus impacting the network lifetime. Vice versa to increase the lifetime of network, number of packet transfer around the nodes should be minimized, thus impacting the synchronization accuracy. A tradeoff can be accomplished by viewing that the packet rate need to be increased only for the part of the network surrounded by events as only those nodes requires high accuracy to collect data. In order to rectify an adversary who aims to tamper with the clock synchronizat...

2025, THEOREM PROVING IN …

Abstract. Higher order logic (HOL) is a modelling language suitable for specifying behaviour at many levels of abstraction. We describe a compiler from a 'synthesisable subset'of HOL function definitions to... more

2025, 2009 Design, Automation & Test in Europe Conference & Exhibition

2025, Proceedings of the Fifth International Conference on Informatics in Control, Automation and Robotics Service

Synchronization of distributed clocks is a critical task in many real time applications over Ethernet. The Ethernet protocol, due to its non-deterministic nature, is not suitable for real-time applications with very strict synchronicity requirements. However, the limit is continuously being pushed outwards by current research. The Precision Time Protocol (PTP), delivered by the IEEE 1588 standard, provides high synchronization accuracy and has been adopted in many real time applications in the areas of industrial automation, measurement & control, communications etc. This paper will discuss several issues aimed at improving the synchronization performance.

2025

A rigorous method for introducing the variational principle describing relativistic ideal hydrodynamic flows with all possible types of discontinuities (including shocks) is presented in the framework of an exact Clebsch type representation of the four-velocity field as a bilinear combination of the scalar fields. The boundary conditions for these fields on the discontinuities are found. We also discuss the local invariants caused by the relabeling symmetry of the problem and derive recursion relations linking invariants of different types. These invariants are of specific interest for stability problems. In particular, we present a set of invariants based on the relativistic generalization of the Ertel invariant.

2025, Lecture Notes in Computer Science

Active measurements are a useful tool for obtaining a variety of Internet metrics. One-way metrics, in general, require the execution of processes at the remote machine and/or machines with synchronized clocks. This work proposes a new algorithm to estimate the first two moments of the one-way delay random variable without the need to access a target machine and to have the machine clocks synchronized. The technique uses the IPID field information and can be easily implemented using ICMP Echo request and reply messages.

2025

Ramsey analysis is applied for the problem of relativistic and quantum synchronization of clocks. Various protocols of synchronization are addressed. Einstein and Eddington special relativity synchronization procedures are considered; quantum synchronization is discussed. Clocks are seen as the vertices of the graph. Clocks may be synchronized or unsynchronized. Thus, introducing of complete, bi-colored, Ramsey graphs, emerging from the lattices of clocks, becomes possible. Transitivity of synchronization plays a key role in the coloring of the Ramsey graph. Einstein synchronization is transitive; whereas, general relativity and quantum synchronization procedures are not. This fact influences the value of the Ramsey number established for the synchronization graph arising from the lattice of clocks. Any lattice built of six clocks, synchronized with quantum entanglement, will inevitably contain the mono-chromatic triangle. Transitive synchronization of logical clocks is discussed. Interrelation between the symmetry of the clock lattice and the structure of the synchronization graph is addressed. The Ramsey analysis of synchronization is important for synchronization of computers in networks and GPS tame-based synchronization.

2025

In a WSN power consumption and congestion are major bottlenecks. These two are inter-related too Power consumption causes several nodes to become dormant and thus increase congestion in the network. Also, congestion leads to abuse of network resources leading increased power consumption. By using adaptive load balancing technique, we reduce the problem of congestion in a network. We improved the traffic splitting protocol (TSP).The proposed method distributes the load in the network to all the nodes in the parallel direction such that no node has a congestion value above threshold. Simulation results have shown the algorithm to be efficient.

2025, EURASIP Journal on Wireless Communications and Networking

Secure time synchronization is a paramount service for wireless sensor networks (WSNs) constituted by multiple interconnected body area networks (BANs). We propose a novel approach to securely and efficiently synchronize nodes at BAN level and/or WSN level. Each BAN develops its own notion of time. To this effect, the nodes of a BAN synchronize with their BAN controller node. Moreover, controller nodes of different BANs cooperate to agree on a WSN global and/or to transfer UTC time. To reduce the number of exchanged synchronization messages, we use an environmental-aware time prediction algorithm. The performance analysis in this paper shows that our approach exhibits very advanced security, accuracy, precision, and low-energy trade-off. For comparable precision, our proposal outstands related clock synchronization protocols in energy efficiency and risk of attacks. These results are based on computations. Photograph © Turisme de Barcelona / J. Trullàs

2025, Proceedings Eighth International Symposium on High Performance Computer Architecture

As clock frequency increases and feature size decreases, clock distribution and wire delays present a growing challenge to the designers of singly-clocked, globally synchronous systems. We describe an alternative approach, which we call a Multiple Clock Domain (MCD) processon in which the chip is divided into several (coarse-grained) clock domains, within which independent voltage and frequency scaling can be per$ormed. Boundaries between domains are chosen to exploit existing queues, thereby minimizing inter-domain synchronization costs. We propose four clock domains, corresponding to the front end (including LI instruction cache), integer units, floating point units, and load-store units (including Ll data cache and L2 cache). We evaluate this design using a simulation infrastructure based on SimpleScalar and Wattch. In an attempt to quantify potential energy savings independent of any particular on-line control strategy, we use of-line analysis of traces from a single-speed run of each of our benchmark applications to identify profitable reconfiguration points for a subsequent dynamic scaling run. Dynamic runs incorporate a detailed model of inter-domain synchronization delays, with latencies for intra-domain scaling similar to the whole-chip scaling latencies of Intel XScale and Transmeta LongRun technologies. Using applications from the MediaBench, Olden, and SPEC2000 benchmark suites, we obtain an average energy-delay product improvement of 20% with MCD compared to a modest 3% savings from voltage scaling a single clock and voltage system.

2025

SDH is a well known technology which is used for the data communication. It is used for high speed data transmission. The synchronization in this technology is with respect to the single clock pulse. So different signals of different data rate are multiplexed by the same clock pulse. This paper is a review paper regarding the problems in synchronisation of the different data rate signals in single clock, and master slave technique used to overcome these problem.

2025, EPiC series in computing

In this paper, we propose a benchmark for verification of properties of fault-tolerant clock synchronization algorithms, namely, a benchmark of a TTEthernet network, where properties of the clock synchronization algorithm as implemented in a TTEthernet network can be verified, and optimization techniques for verification purposes can be applied. Our benchmark, which assumes non-faulty components, aims to be a basis for verifying configurations which include faulty components, information consistency mechanisms, and for verifying other clock synchronization algorithms.

2025, EPiC Series in Computing

In this paper we propose a benchmark for verification of properties of fault-tolerantclock synchronization algorithms, namely, a benchmark of a TTEthernet network, whereproperties of the clock synchronization algorithm as implemented in a TTEthernet network can be verified, and optimization techniques for verification purposes can be applied.Our benchmark, which assumes non-faulty components, aims to be a basis for verifyingconfigurations which include faulty components, information consistency mechanisms, and for verifying other clock synchronization algorithms.

2025

In a non-inertial reference frame in relativity (and all real reference frames are non-inertial; special relativity is just a theoretical abstraction), synchronization by light signals based on the constancy and isotropy of the speed of light do not work. Thus, we must define synchronization by the more fundamental (and, in inertial frames, equivalent) procedure of slowly transporting a clock between two locations: I get out of my chair & travel to yours across the room and make a direct comparison of our watches. In non-inertial reference frames in relativity, I find that the concept of "synchronization" of clocks is path dependent. This means that there is no real concept of synchronization. For example, if clock B is to the north and east of A, they may appear to be synchronized if A travels first to the north, then to the east, while perhaps not if A travels first to the east then to the north. Thus, the question whether A and B "are" synchronized has no definite answer. This has an astonishing consequence for the concepts of (spatially extended) "objects," "observers," and the sense of "self." A spatially extended object (or person or "self") does not exist at what could be meaningfully construed as a single "instant" of time-what is the "now," in light of the forgoing? The concepts of "object" and "self" are interrelated in a sort of feedback loop: which is the chicken, and which is the egg? As Nietzsche said: "How much rudimentary psychology [i.e., street psychology; intuition] resides in your atom, my dear physicists!"

2025, Proceedings of the third conference on Hypercube concurrent computers and applications Architecture, software, computer systems, and general issues -

An efficient interprocessor communication mechanism is essential to the performance of hypercube multiprocessors. All existing hypercube multiprocessors basically support one-to-one interprocessor communication only. However, multi-destination communication (multicast), which is highly demanded in executing many data parallel algorithms, is not directly supported by existing hypercube multiprocessors. A multicast algorithm should attempt to inform each destination in a minimum number of time steps while generating a least amount of traffic. This problem is formally modeled as a graph theoretical problem, the Opfimal Multicast Tree problem. We conjecture that the optimal multicast tree problem remains NP-hard even for hypercube topology. A heuristic greedy multicast algorithm which guarantees a minimized message delivery time is proposed. Simulation results show that the performance of the greedy algorithm is very close to optimal solution. Routing of multicast messages is done in a distributed manner.

2025, arXiv (Cornell University)

The perspective is advanced that the time parameter in quantum mechanics corresponds to the time coordinate in a Minkowski flat spacetime local approximation to the actual dynamical curved spacetime of General Relativity, rather than to an external Newtonian reference frame. There is no incompatibility, as generally assumed in the extensively discussed "problem of time" in Quantum Gravity.

2025, Fusion Engineering and Design

IEEE-1588 over Ethernet protocol is implemented for the synchronization of all clock signals of an ATCA AMC carrier module. The ATCA hardware consists of an AMC quad-carrier main-board with PCI Express switching. IEEE-1588 is to be implemented on a Virtex-6 FPGA. Timing signals on the ATX-AMC4-PTP are managed and routed by a crosspoint-switch implemented on a Virtex-6 FPGA. Each clock signal source may be independently located (on each of the AMC cards, RTM or ATCA backplane).

2025

A common time reference among nodes is one of the key requirements in telecommunication, distributed control systems and industrial automation systems. For instance, 3GPP LTE TDD standard requires at least ±1.5 µsec time accuracy among base stations in order to resolve uplink and downlink transmission. Certain other emerging technologies such as wireless positioning, coordinated antenna beamforming have far more stringent timing requirements often in the order of sub-nanoseconds. For example, in wireless positioning method such as LTE OTDOA [1], every nano-second loss of precision translates into approximately 30 cm of positioning estimation error. In modern packet switched backhaul networks, time distribution protocols are used to distribute timing information from high quality clock source to network nodes. The accuracy and precision of the time distribution protocol improve if it runs as close to hardware as possible so that variable software queuing delays are reduced or eliminated. IEEE 1588-2008 Precision Time Protocol, PTP with hardware timestamping promises higher precision compared to purely software based protocols. However, network asymmetry, variable queuing delays, and timestamping errors in underlying transport, limit the highest time synchronization precision of most commercial PTP deployments to a few hundred nanoseconds. In this work, the operation and estimation capability of IEEE 1588-2008 Precision Time Protocol (PTP) is formally analysed and PTP improvement in the form of super-imposed clock timing aware signal exchange protocol, is proposed. The proposed protocol operating alongside PTP provides independent clock parameter estimates without impacting any existing PTP infrastructure. In addition, it provides relative clock phase offset estimate which is otherwise not detectable through standard PTP. Furthermore, this work through qualitative and quantitative analysis, demonstrates how the supplementary estimates from the proposed method can be used to improve overall clock synchronization accuracy.

2025, IACR Cryptology ePrint Archive

Bitcoin Cash, created in 2017, is a "hard fork" from Bitcoin responding to the need for allowing a higher transaction volume. This is achieved by a larger block size, as well as a new difficulty adjustment (target recalculation) function that acts more frequently (as opposed to Bitcoin's difficulty adjustment happening about every two weeks), resulting in a potentially different target for each block. While seemingly achieving its goal in practice, to our knowledge there is no formal analysis to back this proposal up. In this paper we provide the first formal cryptographic analysis of Bitcoin Cash's target recalculation functions-both ASERT and SMA (current and former recalculation functions, respectively)-against all possible adversaries. The main distinction with respect to Bitcoin's is that they are no longer epoch-based, and as such previous analyses fail to hold. We overcome this technical obstacle by introducing a new set of analytical tools focusing on the "calibration" of blocks' timestamps in sliding windows, which yield a measure of closeness to the initial block generation rate. With that measure, we then follow the analytical approach developed in the Bitcoin backbone protocol [Eurocrypt 2015 and follow-ups] to first establish the basic properties of the blockchain data structure, from which the properties of a robust transaction ledger (namely, Consistency and Liveness) can be derived. We compare our analytical results with data from the Bitcoin Cash network, and conclude that in order to satisfy security (namely, properties satisfied except with negligible probability in the security parameter) considerably larger parameter values should be used with respect to the ones used in practice.

2024, Proceedings of the 4th ACM SIGCOMM conference on Internet measurement

Accurate, reliable timestamping which is also convenient and inexpensive is needed in many important areas including real-time network applications and network measurement. Recently the TSC register, which counts CPU cycles in popular PC architectures, was proposed as the basis of a new software clock which in terms of rate performance performs as well as more expensive GPS alternatives. Smooth and precise clock rate is essential to measure time differences accurately. We show how to define a TSC based clock which is also accurate with respect to absolute time. The clock is calibrated by processing, in a novel way, timestamps contained in the usual flow of Network Time Protocol (NTP) packets between a NTP server and the existing software clock, and TSC timestamps made independently on the host side. Using real measurements over 4 months, validated with a GPS synchronized hardware timing solution, the algorithm measured absolute time with a median error of only 30 microseconds when using a nearby stratum-1 NTP server. Results for two other servers are given. We also provide new algorithms for the robust determination of clock rate. We exploit the reliability of the available hardware to design synchronization algorithms which are inherently robust to many factors including packet loss, server outages, route changes, temperature environment, and network congestion.

2024, IEEE/ACM Transactions on Networking

2024

Modern hardware designs are typically based on multiple clocks. While a singly-clocked hardware design is easily described in standard temporal logics, describing a multiply-clocked design is cumbersome. Thus it is desirable to have an easier way to formulate properties related to clocks in a temporal logic. We present a relatively simple solution built on top of the traditional ltlbased semantics, study the properties of the resulting logic, and compare it with previous solutions.

2024

today it is possible to achieve sub-ns level time synchronization on a wireline network while only us-level synchronization can be achieved on a wireless (microwave) link. In this paper we will, first, study the performances of different time synchronization wireline based protocols, such as Precision Time Protocol (PTP), Synchronous Ethernet (SyncE) and PTP White Rabbit (PTP-WR). And then, we will present our results using a wireless link, and determine which radio technology can achieve ns range time synchronization. Our motivation is to qualify a time transfer process operating over microwave link and offering secured GNSS-like time performance.

2024

Abstract: This paper focuses on the theoretical aspects of clustering techniques in wireless sensor networks, as a mean to improve network lifetime and time synchronization between sensors. Wireless sensor networks (WSNs) are large-scale networks of small low-cost and low-power sensors, to observe and monitor various aspects of physical world. In WSN, data from each sensor is ag-glomerated using data fusion to form a single meaningful result, which makes time synchronization between sensors highly desirable. In this paper, some of the clustering protocols, which have been implemented to improve the network lifetime and clock synchronization, are illustrated. It has been investigated that employing these protocols to select the cluster head results in better performance as compared to non-clustered network and summarize existing clock synchronization protocols based on a palette of factors like precision, accuracy, cost, and complexity.

2024

Mobility is frequently a problem for providing security services in ad hoc networks. In this paper, we render that mobility can alsobe used to enhance security. Specifically, we render that nodes which are in passively monitor traffic in the network can able to detect a Sybil attacker which uses a number of network identities simultaneously. We can do through simulation that this detection can be done by a single node, or multiple trusted nodes can join to improve the accuracy of detection. We then show that although the detection mechanism will falsely identify groups of nodes traveling together as a Sybil attacker, we can extend the protocol to monitor collisions at the MAC level to differentiate between a single attacker spoofing many addresses and a group of nodes traveling in close proximity.

2024, SENSORDEVICES 2021, The Twelfth International Conference on Sensor Device Technologies and Applications

The authors are conducting research and development of different types of sensor systems for the maintenance of civil infrastructures, such as aging bridges and highways, and buildings. Highly accurate time information is added to measurement data, and a set of sensing data that ensures time synchronization is acquired and used for multimodal analysis of risk. In research so far, as a first step, a sensor device was developed that uses a digital high-precision accelerometer to perform highly-accurate time-synchronized sensing of civil infrastructure, such as bridges and highways, and buildings. A vibration table test was performed on the new sensor device, and its time synchronization performance was verified by comparing the measurement results with multiple sensor devices and a servo-type accelerometer. In this paper, a different type of digital sensing platform has been developed that allows a camera sensor to be connected in addition to a digital accelerometer. By adding a unified time stamp synchronized with the absolute time to data from the digital accelerometer and the image from the camera sensor when data is acquired, the vibration and the image can be measured synchronously. First, a Chip-Scale Atomic Clock (CSAC), which is an ultra-high-precision clock, is mounted on the sensor device, and a mechanism is implemented whereby a time stamp is added to the outputs of the digital accelerometer and the camera sensor with timekeeping precision. Since the timekeeping precision of the CSAC is too high, a delay occurs when a time stamp is added by the CPU of the sensor device. Therefore, a Field-Programmable Gate Array (FPGA) dedicated to adding time stamps is prepared. In this paper, the results of a performance verification experiment on a camera sensor mounted on the platform, are described.

2024, SENSORDEVICES 2020, The Eleventh International Conference on Sensor Device Technologies and Applications

The purpose of this research and development is to realize structural health monitoring for increased efficiency in the maintenance of buildings and civil infrastructures, and observations to prepare for natural disasters, such as earthquakes. The most difficult and interesting issue is the realization of inexpensive time-synchronized measurements. It is necessary to install numerous sensors in a building or civil infrastructure and to acquire measured data whose time synchronization is ensured. Although Global Navigation Satellite System (GNSS) time information is generally only available outdoors, the authors designed a system capable of using GNSS time information indoors. This system can deliver time information to a building by using existing TV coaxial cables. The authors further developed a sensor device able to receive indoor GNSS time information and to add highaccuracy time information to measured data. This paper describes the development of a sensor device that adds highaccuracy time information to measured data by using a system to deliver GNSS time information indoors. The performance of the developed sensor device equipped with a mechanism for receiving GNSS signal-based time information was verified from the results of a shaking table experiment. It was shown that it can be applied to structural health monitoring of buildings and civil infrastructure and seismic observation.

2024, IFAC Proceedings Volumes

The Precision Time Protocol specified by IEEE 1588 standard has been proved to be an appropriate network synchronization protocol. The PTP protocol is based on exchanging appropriate timing information, generated by time stamping according to the local clocks, between adjacent clocks. Using the time-stamps, a slave element learns the relation between its own clock and the master clock so that it can synchronize its time to the reference time provided by the master. Uncertainties, e.g., random stamping and quantization errors, greatly affect the synchronization precision. This paper presents a probabilistic state-space model which quantifies the uncertainties and represents the relation between the system variables. Then clock synchronization is posed as a state estimation problem and solved by using Kalman filter. The performance of this approach is verified by numerical results.

2024, 2009 IEEE International Conference on Acoustics, Speech and Signal Processing

Precision Time Protocol (PTP) synchronizes clocks of networked elements by exchanging messages containing precise time-stamps. Based on the available timing information, different algorithms can be developed for the clock synchronization. This paper introduces a novel PTPbased method in which clock synchronization is formulated as a probabilistic inference problem and is solved by Kalman filtering. The performance of this approach is verified by numerical results.