Data retention Research Papers - Academia.edu (original) (raw)

2025, Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip

Chapter 4 showed that supply voltage scaling to the near-threshold (near-V T ) domain is beneficial to improve the nominal retention time of 2T-bitcell GC-eDRAMs, provided that write access occurs only seldom and that the write bit-lines (WBLs) can therefore be driven to a beneficial voltage level during the majority of the time. In this chapter, three novel bitcell circuit and assist techniques to further enhance the retention time of near-V T GC-eDRAMs are presented. The first technique, presented in Sect. 5.2, introduces a novel 3T GC design, characterized by a full NMOS plus PMOS transmission gate as write port. This topology overcomes the drawback of traditional GC-eDRAM implementations that require boosted control signals in order to write full voltage levels to the SN in order to reduce the refresh rate and shorten access times. These boosted voltage levels require either an extra power supply or on-chip charge pumps, as well as nontrivial level shifting and tolerance of high voltage swings. This chapter presents a novel 3T GC-eDRAM bitcell that operates with a single supply voltage and provides superior write capability compared to conventional GC topologies. This is achieved by using a full NMOS plus PMOS transmission gate in the write port and a single NMOS as read transistor. A 2 kb memory macro containing the proposed 3T GC was designed and fabricated in a mature 0.18 µm CMOS process. The test array is powered with a single supply of 900 mV, demonstrating a 0.8 ms worst-case retention time, a 1.3 ns write-access time, and 2.4 pW/bit of retention power. The proposed topology provides a bitcell area reduction of 43% compared to a redrawn 6T SRAM and an overall macro area reduction of 67%. The second technique, expatiated on in Sect. 5.3, is reverse body biasing (RBB) in order to suppress the subthreshold conduction of the write transistor (MW), thereby improving the GC-eDRAM retention time. RBB has previously been applied to conventional 1T-1C DRAM, and, in this context, is also referred to as

2025, IEEE Transactions on Circuits and Systems I: Regular Papers

Gain-cell embedded DRAM (GC-eDRAM) is a possible alternative to traditional static random access memories (SRAM). While GC-eDRAM provides high-density, lowleakage, low-voltage, and inherent2-ported operation, its limited retention time requires periodic, power-hungry refresh cycles. This drawback is further aggravated at scaled technologies, where increased subthreshold leakage currents and decreased in-cell storage capacitances result in faster data integrity deterioration. Therefore, integration of GC-eDRAM within modern systems is often considered to be limited to mature process technologies, where these phenomena are less detrimental. In this paper, we present for the first time a fully functional GC-eDRAM array, implemented and fabricated in a 28-nm process node. The 8-kb array is based on a novel, 2-ported, 4-transistor NMOS-only bitcell with internal feedback to provide efficient operation in the target 28-nm FD-SOI technology. The fabricated memory macro achieves more than 1.6-ms data retention time at 27 °C, which is 30× longer than conventional gain-cell topologies when applied to this technology. The described 4-transistor dual-port nMOS array utilizes over 70% of the total memory macro area, while retaining almost 30% lower cell area than a single-ported 6T SRAM in the same technology.

2025, IEEE Transactions on Circuits and Systems I: Regular Papers

Gain-cell embedded DRAM (GC-eDRAM) is an interesting alternative to SRAM for reasons such as high density, low bitcell leakage, logic compatibility, and suitability for 2-port memories. The major drawbacks of GC-eDRAMs are their limited data retention times (RTs) and the large spread of RT across an array, which degrade energy-efficiency due to refresh cycles. While the array refresh rate can be determined according to circuit simulation or post-manufacturing calibration, there is a lack of analytical and statistical RT models for GC-eDRAM that could unveil the limiters and circuit parameters that lead to the large observed RT spreads. In this work, we derive the first comprehensive analytical model for the statistical distribution of the per-cell retention time of 2T-bitcell GC-eDRAMs, which is found to follow a log-normal distribution. The accuracy of the proposed retention time model is verified by extensive Monte Carlo and worst case distance circuit simulations and silicon measurements of an 0.18 μm test chip. Furthermore, a sensitivity analysis unveils the circuit parameters that have the highest impact on the RT spread. Interestingly, the variability of the threshold voltage of the write access transistor has a much higher impact on the RT spread than the variability of any other circuit parameter, including the storage node capacitor. This holds true under process scaling, for nodes as advanced as 28 nm, as shown through simulation. The insights gained from the retention time model help circuit designers achieve better GC-eDRAMs with longer RTs and sharper RT distributions. In addition, the herein presented model can be used as a basis to study the reliability/energy trade-off for GC-eDRAM usage in fault-tolerant VLSI systems.

2025, 2014 IEEE International Symposium on Circuits and Systems (ISCAS)

Gain-Cell embedded DRAM (GC-eDRAM) has recently been recognized as a possible alternative to traditional SRAM. While GC-eDRAM inherently provides high-density, low-leakage, low-voltage, and 2-ported operation, its limited retention time requires periodic, power-hungry refresh cycles. This drawback is further enhanced at scaled technologies, where increased subthreshold leakage currents and decreased in-cell storage capacitances result in faster data deterioration. In this paper, we present a novel 4T GC-eDRAM bitcell that utilizes an internal feedback mechanism to significantly increase the data retention time in scaled CMOS technologies. A 2 kb memory macro was implemented in a low-power 65 nm CMOS technology, displaying an over 3× improvement in retention time over the best previous publication at this node. The resulting array displays a nearly 5× reduction in retention power (despite the refresh power component) with a 40% reduction in bitcell area, as compared to a standard 6T SRAM.

2025, IEEE Transactions on Circuits and Systems II: Express Briefs

Gain cells have recently been shown to be a viable alternative to SRAM in low-power applications due to their low leakage currents and high density. The primary component of power consumption in these arrays is the dynamic power consumed during periodic refresh operations. Refresh timing is traditionally set according to a worst-case evaluation of retention time, under extreme process variations and worst-case access statistics, leading to frequent, power hungry refresh cycles. In this paper, we present a replica technique for automatically tracking the retention time of a gain cell embedded DRAM macrocell according to process variations and operating statistics, thereby reducing the data retention power of the array. A 2 kb array was designed and fabricated in a mature 0.18µm CMOS process, appropriate for integration in ultra-low power applications, such as biomedical sensors. Measurements show efficient retention time tracking across a range of supply voltages and access statistics, lowering the refresh frequency by more than 5×, as compared to traditional worst-case design.

2025, EURASIP Journal on Advances in Signal Processing

Non-volatile resistive memories, such as phase-change RAM (PRAM) and spin transfer torque RAM (STT-RAM), have emerged as promising candidates because of their fast read access, high storage density, and very low standby power. Unfortunately, in scaled technologies, high storage density comes at a price of lower reliability. In this article, we first study in detail the causes of errors for PRAM and STT-RAM. We see that while for multi-level cell (MLC) PRAM, the errors are due to resistance drift, in STT-RAM they are due to process variations and variations in the device geometry. We develop error models to capture these effects and propose techniques based on tuning of circuit level parameters to mitigate some of these errors. Unfortunately for reliable memory operation, only circuit-level techniques are not sufficient and so we propose error control coding (ECC) techniques that can be used on top of circuit-level techniques. We show that for STT-RAM, a combination of voltage boosting and write pulse width adjustment at the circuit-level followed by a BCH-based ECC scheme can reduce the block failure rate (BFR) to 10 -8 . For MLC-PRAM, a combination of threshold resistance tuning and BCH-based product code ECC scheme can achieve the same target BFR of 10 -8 . The product code scheme is flexible; it allows migration to a stronger code to guarantee the same target BFR when the raw bit error rate increases with increase in the number of programming cycles.

2025, IEEE Electron Device Letters

Low current leakage characteristics of a novel silicon-on-insulator (SOI) device are investigated in view of application to a gain-cell dynamic random access memory (DRAM). The device consists of a two-layered poly-Si gate. Since, in this device, the memory node is electrically formed by the gate in undoped SOI wire, no p-n junction is required. The retention is found to be dominated by the subthreshold leakage, which leads to long data retention. The device also achieved a fast (10 ns) writing time and its fabrication process is compatible with those of SOI MOSFETs. The present results, thus, strongly suggest a way of conducting a gain-cell DRAM to be embedded into logic circuits.

2025

With the development and the spread of Internet of Things (IoT) technologies, various types of data are generated for IoT applications anywhere and anytime. We defined such data that depends heavily on generation time and location as Spatio-Temporal Data (STD). In the previous works, we have proposed the data retention system using vehicular networks to achieve the paradigm of “local production and consumption of STD.” The system can provide STDs quickly for users within a specific location by retaining the STD within the area. However, the system does not consider that each STD has different requirements for the data retention. In particular, the lifetime of the STD and the diffusion time to the whole area directly influence to the performance of data retention. Therefore, we propose a dynamic control of data transmission interval for the data retention system by considering the requirements. Through the simulation evaluation, we found that our proposed method can satisfy the requi...

2025, 2012 4th Asia Symposium on Quality Electronic Design (ASQED)

have recently gained their popularity in embedded applications because of their high density and good voltage margin. The most important design requirements in eDRAM cells are cell area, data retention time and read speed. In this paper, we present an in-depth analysis on the data retention time of various logiccompatible eDRAM cells, followed by the effects of several design factors on the retention time. A systematic methodology is proposed for enhancing the retention time of the eDRAM cells. Simulation results using a standard 65nm CMOS technology show that the optimization process improves the data retention time more than 3×. Finally, the number of read operations per retention period is estimated to show the effectiveness of each eDRAM cell. Analysis demonstrates that although the 2T eDRAM cell has a shorter retention time than the conventional 3T cell, it has better effectiveness due to the faster read operation.

2025, arXiv (Cornell University)

Memory has always been a building block element for information technology. Emerging technologies such as artificial intelligence, big data, the internet of things, etc., require a novel kind of memory technology that can be energy efficient and have an exception data retention period. Among several existing memory technologies, resistive random-access memory (RRAM) is an answer to the above question as it is necessary to possess the combination of speed of RAM and nonvolatility, thus proving to be one of the most promising candidates to replace flash memory in next-generation non-volatile RAM applications. This review discusses the existing challenges and technological advancements made with RRAM, including switching mechanism, device structure, endurance, fatigue resistance, data retention period, and mechanism of resistive switching in inorganic oxides material used as a dielectric layer. Finally, a summary and a perspective on future research are presented.

2025, Diario Constitucional

¿qué dice? La Resolución Exenta Número 566 publicada el 6 de abril de 2024, promulgada el 28 de marzo del mismo año y cuya última modificación es del 4 de febrero de 2025, merece un poco de atención. Observar dicha resolución a la luz del nuevo régimen de protección y tratamiento de datos personales resulta imperativo por, al menos, dos razones: para observar eventuales problemas normativos y para reflexionar sobre el rol de la regulación en sociedades con una alta densidad empresarial y desarrollo de industrias. Lo primero es sintetizar la resolución, a fin de comprender sumariamente lo que pretende establecer: Respecto de su aplicación: son objeto de esta regulación procesos que llevan a cabo proveedores de servicios de telecomunicaciones, con motivo de la celebración, modificación y término de un contrato así como otros actos que puedan traducirse en obligaciones a interesados o suscriptores , tales como venta y entrega de equipos y activación de tarjetas SIM (Artículo 1º), en la medida que el cobro de este último se efectúe en el documento de cobro emitido por su proveedor, deberá realizarse, contemplando al menos uno de los siguientes estándares de seguridad para efectos de la validación de identidad, sin importar el canal de atención utilizado (presencial, telefónico o virtual) del que se trate (Artículo 2º). Estándares de seguridad que deben aplicarse: Primera opción, Artículo 2º, letra a): Solicitar la cédula de identidad o pasaporte vigentes del solicitante y verificar la identidad de éste mediante biometría de huella dactilar viva, capturándola y comparándola con la huella registrada por el Servicio de Registro Civil e Identificación en dicha cédula o pasaporte vigente, o en las bases de datos de los proveedores de servicios de biometría, debiendo dar cumplimiento a las disposiciones legales, reglamentarias y normas especiales que regulen la protección de la vida privada. Nótese que esta opción establece la solicitud de cédula más la comprobación biométrica por huella dactilar; se utiliza el vocablo conjuntivo "y" mas no el disyuntivo "o". En consecuencia, la primera opción considera la concurrencia copulativa de la solicitud de cédula más la comprobación biométrica por huella dactilar. Segunda opción, Artículo 2º, letra b): Verificar la identidad o el pasaporte vigente del solicitante mediante biometría facial, validando la coincidencia entre la captura de la fotografía de la cédula de identidad y el rostro escaneado, efectuando prueba de detección de vida y descartando la suplantación hecha con, a lo menos: fotos, videos, cambio de imágenes, proyección de videos o máscaras.

2025, Third Parties in Criminal Proceedings. A Comparative Law Study

This study proposes a comparative constitutional analysis on the safeguard of third parties' fundamental rights in criminal proceedings. Specifically, the essay focuses on the regulations that have been adopted by the countries whose legal systems have been commented on in this book, stressing their merits and limitations and the way such provisions could be modified in order to protect these subjects' rights. Moreover, the study theorises a possible balance between investigative needs and the safeguard of third parties' fundamental rights.

2025

The NS-Melde-und Personenstandsgesetze [Meldegesetz and Personenstandsgesetz] have established a system of surveillance and data collection that significantly restricts the personal freedom of citizens. Originating in the Third Reich, these laws institutionalized practices of monitoring and controlling the population, laying the groundwork for contemporary privacy violations. In this paper, we critically analyze how these laws have led to the misuse of metadata and violated the rights of citizens.

2025, Electronics Letters

2025

2025, IEEE Transactions on Circuits and Systems I-regular Papers

2025, Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip

2025, IEEE Transactions on Circuits and Systems I: Regular Papers

2025, 2014 IEEE International Symposium on Circuits and Systems (ISCAS)

2025, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015

Current variation aware design methodologies, tuned for worst-case scenarios, are becoming increasingly pessimistic from the perspective of power and performance. A good example of such pessimism is setting the refresh rate of DRAMs according to the worst-case access statistics, thereby resulting in very frequent refresh cycles, which are responsible for the majority of the standby power consumption of these memories. However, such a high refresh rate may not be required, either due to extremely low probability of the actual occurrence of such a worst-case, or due to the inherent error resilient nature of many applications that can tolerate a certain number of potential failures. In this paper, we exploit and quantify the possibilities that exist in dynamic memory design by shifting to the so-called approximate computing paradigm in order to save power and enhance yield at no cost. The statistical characteristics of the retention time in dynamic memories were revealed by studying a fabricated 2 kb CMOS compatible embedded DRAM (eDRAM) memory array based on gain-cells. Measurements show that up to 73% of the retention power can be saved by altering the refresh time and setting it such that a small number of failures is allowed. We show that these savings can be further increased by utilizing known circuit techniques, such as body biasing, which can help, not only in extending, but also in preferably shaping the retention time distribution. Our approach is one of the first attempts to access the data integrity and energy tradeoffs achieved in eDRAMs for utilizing them in error resilient applications and can prove helpful in the anticipated shift to approximate computing.

2025, IEEE Transactions on Circuits and Systems Ii-express Briefs

2025, SSRN Electronic Journal

In Digital Rights Ireland Ltd v Minister for Communications, the European Court of Justice found the EU Data Retention Directive, which required the retention of communications data for up to two years, to be incompatible with Articles 7 and 8 of the EU Charter of Fundamental Rightsthe rights to privacy and to the protection of personal data. It is argued in this note that the decision ought to be taken as one that is concerned with the exercise of arbitrary power, a concern that is captured by the concept of domination. *Melbourne Law School. I am grateful to my colleague Chantal Morton and an anonymous reviewer for providing valuable comments on earlier drafts of this note.

2024

Artigo publicado na "Revista do CEJUR/TJSC: Prestação Jurisdicional", v. 12, p. e0433, 2024.

2024, Journal of Applied Physics

Transient capacitances were numerically investigated for Ge/ Si heteronanocrystal memories. Flatband voltage shifts ͑⌬V fb ͒ were obtained. The results suggest that the Ge/ Si heteronanocrystal memories have significantly longer data retention compared with the memories embedding Si nanocrystals only. It is also found that larger heteronanocrystal leads to longer retention, larger device capacitance, and smaller ⌬V fb .

2024, Journal of Applied Physics

Transient capacitances were numerically investigated for Ge∕Si heteronanocrystal memories. Flatband voltage shifts (ΔVfb) were obtained. The results suggest that the Ge∕Si heteronanocrystal memories have significantly longer data retention compared with the memories embedding Si nanocrystals only. It is also found that larger heteronanocrystal leads to longer retention, larger device capacitance, and smaller ΔVfb.

2024, 2017 22nd IEEE European Test Symposium (ETS)

Increasing the number of bits per cell and technology scaling are ways to reduce the cost per gigabyte of flash memories and solid-state drives (SSDs). Unfortunately, this trend has a negative impact on data retention capability and cycling endurance. Periodic data refresh allows dealing with a reduced retention time and, indirectly, may be used to improve cycling endurance. A worst case data refresh frequency is not optimal in the presence of important temperature variations as it may become unnecessarily pessimistic and alter the SSD response latency and energy consumption. Here, a flexible data refresh methodology is proposed based on approximations of the Arrhenius-curves employed to describe the temperature impact on the retention capability of flash memories. These approximations may be implemented with the help of a small module called Atimer. For an asymmetric temperature distribution between 30°C and 70°C, it is estimated that the refresh frequency can be reduced by more than 63× and almost 3× for respectively charge detrapping and SILC failure mechanisms.

2024, IEEE Journal of the Electron Devices Society

A hydrogenated amorphous silicon thin-film transistor with an engineered charge-trapping interface between the gate dielectric and the channel layer is fabricated to realize non-volatile memory. The memory devices possessed a large memory window and good endurance with an estimated 5-year lifetime. The charge retention lifetime under persistent read bias conditions was found to be~50% less compared to floating conditions. Measured results indicate the importance of continuous read cycles for estimating the device lifetime and the need for a larger memory window to extend memory operation lifetime. INDEX TERMS Hydrogenated amorphous silicon (a-Si:H), thin-film transistor (TFT), non-volatile memory, charge trapping.

2024, 2014 IEEE 6th International Memory Workshop (IMW)

In this paper the effect of SET temperature on dataretention performances in HfO2-based RRAM has been thoroughly investigated. We demonstrated, for the first time to our knowledge, that high temperature programming (even if it has no influence on the initial resistance) has a strong effect on thermal stability of the conductive filaments. Moreover, we highlighted the impact of SET temperature also on RESET characteristics. We gathered all these experimental evidences under a simple modeling of the filament morphology, proving that the filament size might be tuned by adjusting the programming temperature. We conclude that reducing the conductive filament diameter while keeping high density of the oxygen vacancies significantly improves data retention.

2024, International Journal of Engineering, Management and Humanities (IJEMH)

In our data-driven era, managing information efficiently throughout its lifecycle is crucial. Applications like SAP store enterprise information that must be retained due to regulatory and statutory requirements, particularly with SAP ERP. As SAP S/4 HANA emerges, many organizations are upgrading from their legacy SAP ERP system to SAP S/4 HANA. Keeping retired applications like SAP ECC incurs hardware and software costs. SAP Information Lifecycle Management (ILM) provides a structured approach to data retention, compliance, and cost management. This article examines the need, functionality, and benefits of SAP ILM, featuring a literature review, comparative analysis, and case studies of real companies leveraging this technology.

2024, Forensic science international

In 2008, the European Court of Human Rights, in S and Marper v the United Kingdom, ruled that a retention regime that permits the indefinite retention of DNA records of both convicted and non-convicted ("innocent") individuals is disproportionate. The court noted that there was inadequate evidence to justify the retention of DNA records of the innocent. Since the Marper ruling, the laws governing the taking, use, and retention of forensic DNA in England and Wales have changed with the enactment of the Protection of Freedoms Act 2012 (PoFA). This Act, put briefly, permits the indefinite retention of DNA profiles of most convicted individuals and temporal retention for some first-time convicted minors and innocent individuals on the National DNA Database (NDNAD). The PoFA regime was implemented in October 2013. This paper examines ten post-implementation reports of the NDNAD Strategy Board (3), the NDNAD Ethics Group (3) and the Office of the Biometrics Commissioner (OBC) (4...

2024

With continued scaling of NAND flash memory process technology and multiple bits programmed per cell, NAND flash reliability and endurance are degrading. In our research, we experimentally measure, characterize, analyze, and model error patterns in nanoscale flash memories. Based on the understanding developed using real flash memory chips, we design techniques for more efficient and effective error management than traditionally used costly error correction codes. In this article, we summarize our major error characterization results and mitigation techniques for NAND flash memory. We first provide a characterization of errors that occur in 30-to 40-nm flash memories, showing that retention errors, caused due to flash cells leaking charge over time, are the dominant source of errors. Second, we describe retention-aware error management techniques that aim to mitigate retention errors. The key idea is to periodically read, correct, and reprogram (in-place) or remap the stored data before it accumulates more retention errors than can be corrected by simple ECC. Third, we briefly touch upon our recent work that characterizes the distribution of the threshold voltages across different cells in a modern 20-to 24-nm flash memory, with the hope that such a characterization can enable the design of more effective and efficient error correction mechanisms to combat threshold voltage distortions that cause various errors. We conclude with a brief description of our ongoing related work in combating scaling challenges of both NAND flash memory and DRAM memory.

2024

With the continued scaling of NAND flash and multi-level cell technology, flash-based storage has gained widespread use in systems ranging from mobile platforms to enterprise servers. However, the robustness of NAND flash cells is an increasing concern, especially at nanometer-regime process geometries. NAND flash memory bit error rate increases exponentially with the number of program/erase cycles. Stronger error correcting codes (ECC) can be used to tolerate higher error rates, but these have diminishing returns with increasing P/E cycles and can have prohibitively high power, area, and latency overheads. The goal of this paper is to develop new techniques that can tolerate high bit error rates without requiring prohibitively strong ECC. Our techniques, called Flash Correct-and-Refresh (FCR) exploit the observation that the dominant error source in NAND flash memory is retention errors, caused by flash cells losing charge over time. The key idea is to periodically read, correct, and reprogram (in-place) or remap the stored data before it accumulates more retention errors than can be corrected by simple ECC. Detailed simulations of a solid-state drive (SSD) storage system driven by measured experimental data from error characterization on real flash memory chips show that our techniques provide 46x average lifetime improvement on a variety of workloads at no additional hardware cost. We also find that our techniques achieve lifetime improvements that cannot feasibly be achieved with stronger ECC.

2024, 2012 4th Asia Symposium on Quality Electronic Design (ASQED)

2024

“La difesa del diritto non è arte retorica ma coscienza civile e impegno nella vita.”cit.
Accolta la tesi interpretativa della difesa del ricorrente (che pubblica il post), da parte delle Sezioni Unite, a sostegno del tradizionale orientamento della Cassazione che ha sempre escluso la condanna alle spese nel procedimento di correzione degli errori materiali.
Dal 14/11/2024 il principio di diritto fino al 13/11/2024 vigente (oggetto di contrasto e dibattiti accesi in dottrina e giurisprudenza) è stato così “ristrutturato” dalle Sezioni Unite: «Nel procedimento di correzione degli errori materiali, ex artt. 287-288 e 391-bis cod. proc. civ., in quanto di natura sostanzialmente amministrativa e non diretto a incidere, in situazione di contrasto tra le parti, sull’assetto di interessi già regolato dal provvedimento corrigendo, non può procedersi alla liquidazione delle spese, non essendo configurabile in alcun caso una situazione di soccombenza, ai sensi e per gli effetti di cui all’art. 91 cod. proc. civ., neppure nella ipotesi in cui la parte non richiedente, partecipando al contraddittorio, opponga resistenza all’istanza».

2024, Solid-State Electronics

SANOS technology is the first time accurately analyzed and modeled. Firstly, the retention is studied on capacitors to determine the main retention mechanisms. The electron detrapping in the silicon nitride, followed by tunneling through the aluminum oxide is found to be the dominant mechanism causing the retention loss. The modeling of this effect reproduces the observed temperature, gate work function and window dependency. Secondly, these results are applied to scaled devices where the retention is dominated by the same mechanisms. The difference in the retention loss between capacitors and devices is explained by a different field distribution in the gate dielectric. Thirdly, the issue of lateral redistribution occurring at high temperature in scaled transistors is analyzed by 2D simulations and retention tests in SONOS devices.

2024, ERCIM News

The continuous success of NAND flash is a result of the enormous progress achieved over the past few decades. Initially driven by the scaling of the process technology node, then assisted by an increase in the number of bits stored per cell, today, the aggressive stacking of layers in the third dimension continues to preserve this trend. Read and write operations are performed on a page granularity – where the page size is currently in the order of 16KiB – with several hundred pages being organised into a block. But an entire block must be erased prior to being programmed. Therefore, Flash controllers run a Flash translation layer (FTL), that transforms “writes” into a sequential write stream and maintains the mapping between logical and physical pages.

2024, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)

The reliability of multilevel analog memory is mainly determined by data retention, cycling endurance, and read and write disturb. This storage system retains a voice message for 10 years and can record continuously for 50K cycles. It can tolerate up to 300 single cell retention shifts > 50 mV and still meet THD < 0.5% and SINAD > 32 dB. ' ' ' """ ' ' """' ' ' ' """ ' '

2024, 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

We propose a vertical gate all around 1-transistor DRAM cell with silicon channel and gallium phosphide source drain (GaP-SD) as a viable alternative to the present 1T-1C DRAM technology. The valence band offset at GaP and Si interface helps to store more holes in the transistor body and thus improves the retention time by 2 order over conventional Si-SD 1T DRAM. By examining body thickness variability, we conclude that GaP-SD memory cell can withstand the performance degradation due to device variability to meet the ITRS retention time requirements. Finally the GaP-SD memory cell is optimized for scaled dimensions upto 20nm body thickness to establish its superiority at lower technology nodes.

2024, IEEE access

In recent years, the energy consumption of IoT edge nodes has significantly increased due to the communication process. This necessitates the need to offload more computation to the edge nodes to minimize data transmission over the network. To achieve this, higher-performance CPUs and memory are required on the edge nodes. In this context, we propose an energy-efficient memory architecture specifically designed for edge nodes. STT-MRAM is a promising memory technology that offers potential replacements for SRAM and Flash in IoT devices. STT-MRAM exhibits notable advantages over traditional memory technologies, such as non-volatility for data retention without continuous power supply and energy efficiency, resulting in extended battery life for portable devices and IoT applications. Its potential for higher memory density and scalability through standard fabrication processes further enhances its appeal for next-generation memory solutions. However, the high write energy consumption is its main disadvantage. Previous works have explored non-volatility relaxation in CPU cache but there is a need to extend this approach to main memory in IoT devices. In this paper, we propose a multi-retention STT-MRAM architecture for IoT main memory. Additionally, we propose a memory mapping scheme for the suggested memory architecture and examine the impact of more relaxed retention levels on energy consumption. To the best of our knowledge, this is the first study to thoroughly investigate the optimal thermal stability factor value for STT-MRAM in IoT applications while also considering optimal memory mapping. The proposed architecture reduces energy consumption by an average of 70% and up to 83% compared to the currently used non-volatile STT-MRAM architecture. Furthermore, we propose two memory mappings that are easy to use and achieve an average energy savings that is just 5% away from the ideal mapping.

2024

Due to fast technological development and our constant communication protection of communication privacy in every aspect of our (legal) life has become more important than ever before. Regarding protection of privacy in criminal procedure special emphasis should be given to the regulation of privacy in Slovenian Constitution and its interpretation in the case law of the Constitutional Court. This paper presents the definition of privacy and communication privacy in Slovenian constitutional law and exposes the main issues of communication privacy that have been discussed in the case law of the Constitutional Court in the last twenty years. Thereby the paper tries to show the general trend in the case law of Constitutional Court regarding the protection of communication privacy and to expose certain unsolved issues and unanswered challenges. Slovenian constitutional regulation of communication privacy is very protective, considering the broad definition of privacy and the strict conditions for encroachment of communication privacy. The case law of Slovenian Constitutional Court has also shown such trend, with the possible exception of the recent decision on a dynamic IP address. The importance of this decision is however significant, since it could be applicable to all forms of communication via internet, the prevailing form of communication nowadays. Certain challenges still lay ahead, such as the current proposal for the amendment of Criminal Procedure Act-M, which includes the use of IMSI catchers and numerous unanswered issues regarding data retention after the decisive annulment of its partial legal basis by the Constitutional Court.

2024

Obligation for telecom operators to retain traffic and location data for combating crime purposes had been controversial ever since the adoption of the Data Retention Directive in 2006 because of its inherent negative impact on the fundamental right to privacy and personal data protection. However, the awaited judgment of the CJEU in April this year, which declared the Directive invalid, did not so far resolve the ambiguity of the issue. Namely, having in mind that half a year later, some countries did not amend their national data retention legislations (yet) to comply with the aforementioned CJEU judgment, telecom operators as addresses of this obligation are in uncertain legal situation which could be called “lose-lose” situation. Also, the emphasis from the question of proportionality between data privacy and public security is shifted to the question of existence of valid legal basis for data processing (retaining data and providing them to authorities) in the new legal environ...

2024, 2008 IEEE International SOI Conference

2024

For a concise, interactive synopsis of the impact of surveillance culture, the Snowden leak and the virtual impossibility of avoiding surveillance in modern society, see Rory Cellan-Jones, Who's Watching Me on the Internet?, BBC iWonder (2016) available at http://www.bbc.co.uk/guides/zyvmhv4, accessed 21 May 2016. 2 See Jon Henley and Kareem Shaheen , Suicide bombers in Brussels had known links to Paris attacks, The Guardian, (March 23, 2016). 3 The Investigatory Powers Bill 2015, HC Bill 143, perhaps tellingly commonly referred to in the media as 'the Snooper's Charter'. See Rowena Mason, Anushka Asthana and Alan Travis, 'Snooper's charter': Theresa May faces calls to improve bill to protect privacy, The Guardian, (March 15, 2016), accessed April 27,2016. 4 European Convention of Human Rights. 5 HOME OFFICE, INVESTIGATORY POWERS BILL-EUROPEAN CONVENTION ON HUMAN RIGHTS MEMORANDUM, (March 8, 2016), available at https://www.gov.uk/government/publications/investigatorypowers-bill-overarching-documents (last accessed May 11,2016).

2024, Central European Conference on Information and Intelligent Systems: Proceedings

According to the EU Charter of Fundamental Rights, both the right to privacy and the right to the protection of personal information are different, emancipated rights that are complementary to one another. The high level of data protection was further improved by the General Data Protection Regulation. Open data is information that may be used for commercial or non-commercial purposes and is made accessible to the public in an open and machinereadable manner. It is anticipated that open data would increase public sector openness while also fostering the (data) economy and data-driven innovations, particularly with regard to the IT services sector and SMEs. The Open Data Directive has established rules for the release of open data and the re-use of public sector information in the EU. The new European data strategy from 2020 has underlined the necessity for open data, even outside of the data owned by the public sector. According to this strategy, the EU's single market for data will be strengthened by using more open data. Consequently, the EU has adopted the new Data Governance Act as a crosssectoral instrument that tries to increase data accessibility by regulating the reuse of protected data held by public sector, promoting the sharing of data for altruistic purposes and regulating data intermediaries as a novel approach to fostering open data economy. 1

2024

The British population has been greatly affected by the rapid evolution in information and communications technology. In this digital society, we all leave extensive traces of our behaviour and interactions in the course of our normal, everyday lives. We have unprecedented opportunities to express ourselves, to connect and share knowledge, to be prosperous and inventive. At the same time, the digital society also presents new challenges, making citizens potential targets for fraudsters, criminals and possibly terrorists. The task for the police and SIAs has become more demanding as they try to stay abreast of rapid technological innovation and deal with threats that emanate from across the globe. It is important to ensure that the powers granted to these agencies to protect the public are explicit, comprehensible, and are seen to be both lawful and consistent with democratic values. The citizen’s right to privacy online as offline – and what constitutes a ‘justifiable’ level of intr...