Digital Signal Processors Research Papers (original) (raw)

2025, IEEE Transactions on Energy Conversion

Superconducting magnetic energy storage (SMES) has been under development for electric system applications for some time. Large units (210 MWh) have been designed for electric load management. Small systems (<10MW) have been designed for power quality enhancements. Small systems, in particular, can provide momentary wfyover on a distribution network, thus avoiding outages in customers' electric supply. The price of today's small units is relatively expensive. The objective of this study was to evaluate possible cost reductions of small SMES devices to determine long-term feasibility for use INTRODUCTIO N in utility's systems.

2025, IEEE Transactions on Instrumentation and Measurement

Electrochemical impedance spectroscopy (EIS) is recognized to be a powerful and noninvasive technique to test the integrity of protective coatings on memorials, but commercial EIS systems are rather costly though versatile devices. This paper describes a low cost and portable EIS system that is based on a compact digital signal processor (DSP) board and embeds the potentiostatic function so that it can be used without requiring an external potentiostat. The software that runs on the DSP is designed to analyze the electrochemical impedance only in a reduced frequency range in order to produce a simple corrosion alert result. The device is equipped with a digital interface and can be connected to a personal computer to carry out a complete frequency analysis and perform a more complex data processing.

2025, 31st Annual Frontiers in Education Conference. Impact on Engineering and Science Education. Conference Proceedings (Cat. No.01CH37193)

2025, IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Power is becoming a critical constraint for designing embedded applications. Current power analysis techniques based on circuit-level or architectural-level simulation are either impractical or inaccurate to estimate the power cost for a given piece of application software. In this paper, an instruction-level power analysis model is developed for an embedded DSP processor based on physical current measurements. Signi cant points of di erence have been observed between the software power model for this custom DSP processor and the power models that have been developed earlier for some general-purpose commercial microprocessors 1, 2]. In particular, the e ect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the processor has special architectural features that allow dual-memory accesses and packing of instructions into pairs. The energy reduction possible through the use of these features is studied. The on-chip Booth multiplier on the processor is a major source of energy consumption for DSP programs. A microarchitectural power model for the multiplier is developed and analyzed for further power minimization. In order to exploit all of the above e ects, a scheduling technique based on the new instruction-level power model is proposed. Several example programs are provided to illustrate the e ectiveness of this approach. Energy reductions varying from 26% to 73% have been observed. These energy savings are real and have been veri ed through physical measurement. It should be noted that the energy reduction essentially comes for free. It is obtained through software modi cation, and thus, entails no hardware overhead. In addition, there is no loss of performance since the running times of the modi ed programs either improve or remain unchanged.

2025, IEEE Journal of Solid-State Circuits

Complex DSP ASIC's typically feature high-quality filters implemented as dedicated blocks. FIDYS (FIlter 1Di synthesis System) is a new VLSI recursive filter compiler, specifically designed to meet those needs. It is fully integrated from behavioral frequency template specifications down to layout. It comprises a specific approximation and synthesis procedure, the generation of a systolic architecture with parameterized pipelining based on dedicated bit-serial operators, and final generation of a densely packed layout based on a minimal dedicated set of 1-km CMOS basic cells. A new lossless discrete integrator (LDI) ladder filter structure is used. It features an outstanding low sensitivity and a high degree of modularity and regularity that directly result in streamlined hardware and an efficient placement with minimal routing overhead. Examples of representative applications for telecommunications circuits are presented. A cuits integrating a whole system are becoming customary in many application areas such as ISDN telecommunications. These circuits typically implement a highly heterogeneous set of loosely connected algorithmic subtasks. A fast and efficient design for the whole circuit is best achieved through the joint use of a family of specific silicon compilation or silicon assembly tools. each of which addresses a distinct class of these computations. Such a set of tools is being developed at CNET-Grenoble, based on a common layout generation language [I]. VLSI blocks separately generated in this way are then easily assembled to make up a "system on a chip." No single general-purpose silicon compiler is presently able to achieve the same design performance as such a "multicompiler" approach. Manuscript

2024, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)

This paper presents an analytical framework for the implementation of digital infinite impulse response filters in fixed-point hardware on field programmable gate arrays. This analysis is necessary because FPGAs, unlike fixed register size digital signal processors, allow custom bit widths. Within the framework, the designer determines the number of bits necessary for representing the constant coefficients and the internal signals in the filter. The coefficient bit widths are determined by accounting for the sensitivity of the filter's pole and zero locations with respect to the coefficient perturbations. The internal signal bit widths are determined by calculating theoretical bounds on the ranges of the signals, and on the errors introduced by truncation in the fixed-point hardware. The bounds tell how many bits are required at any point in the computation in order to avoid overflow and guarantee a prescribed degree of accuracy in the filter output. The bounds form the basis for a methodology for the fixed-point digital filter implementation. The methodology is applied to the implementation of a second-order filter used as a compensator in a magnetic bearing control system.

2024, IEEE Power Electronics Letters

2024, Studies in Informatics and Control

Induction heating is a very complex process that involves multi-physics couplings such as electromagnetic, thermal and mechanical. Its application permits to heat a ferromagnetic work piece with better heat distribution, more accuracy and low power consumption [1]-[2]. Recently, a full bridge series-parallel resonant inverter with AVC control strategies is the most widely used topology due to its high reliability. This structure can deliver three level output voltage from DC input voltage [3]-[8].

2024, IEEE Transactions on Communications

2024, Journal of Systems Architecture the Euromicro Journal

A high-performance configurable multi-channel counter is presented. The system has been implemented on a smallsize and low-cost Commercial-Off-The-Shelf (COTS) FPGA/DSP-based board, and features 64 input channels, a maximum counting rate of 45 MHz, and a minimum integration window (time resolution) of 24 µs with a 23 b counting depth. In particular, the time resolution depends on both the selected counting bit-depth and the number of actually used channels: indeed, with a 8 b counting depth, the time resolution reaches the value of 8 µs if all the 64 input channels are enabled, whereas it lowers to 378 ns if only 2 channels are used. Thanks to its flexible architecture and performance, the system is suitable in highly demanding photon counting applications based on SPAD arrays, as well as in many other scientific experiments. Moreover, the collected counting results are both real-time processed and transmitted over a high-speed IEEE 1394 serial link. The same link is used to remotely set up and control the entire acquisition process, thus giving the system a even higher degree of flexibility. Finally, a theoretical model which immediately provides the overall system performance is described. The model is subsequently validated by the reported test results.

2024, International Journal of Power Electronics and Drive Systems (IJPEDS)

The fluctuation of grid variables affects the performance of the phase-locked loop, considerably reducing the efficiency of grid energy injection or compensation currents generation during active filtering. The phase locked loop is the main tool for grid synchronization, offering continuous, real-time extraction of grid variables. As these techniques are implemented on digital computers, their discretization and analysis of resource requirements is an important step. This work represents a discretization and implementation on a digital signal processing (DSP) board of two distinct phase-locked loop (PLL) techniques as well as a comparative study of the latter. Our study covers various aspects, including the discretization of the PLLs to be studied, an assessment of the hardware resources required, their implementation on a DSP board, and their effectiveness in quickly identifying grid variables in the presence of imbalance and harmonics, which represent the most frequent grid imperfections.

2024, IEEE Signal Processing Magazine

Sigma-delta modulation (Σ∆M) techniques provide a range of opportunities in a signal processing system for both increasing performance and datapath optimization along the siliconarea axis in the design space. Σ∆M technology, together with FPGA based signal processing hardware, can be combined to produce creative, high-performance and area efficient solutions to many signal processing problems.This paper presents several such examples. Σ∆M based DSP is employed to generate FPGA hardware implementations of narrow-band filters, a DC canceler and hybrid digital-analog control loops for a software defined radio architecture.

2024, International Journal of Advances in Scientific Research and Engineering

Induction motors are widely utilized in various industries because of simplicity in service, durability, and low cost, leading to the displacement of DC motors. However, control system challenges have hindered their full potential for high performance. Many low-performance drives utilize scalar control, which adjusts only the stator magnitudes to uphold a persistent stator flux. Vector control emerged to address this limitation by enabling induction motor control analogous to DC motors. Subsequently, Direct Torque Controlled (DTC) induction motor drives were developed. Unlike vector-controlled drives where stator currents serve as control variables, DTC controls stator flux linkages. DTC employs a Reference Flux (RF) estimator to determine RF based on motor speed and a PI controller to estimate reference torque using speed error as input. The calculated stator flux angle determines the sector number for generating switching signals, traditionally done through a RF estimator. This estimator has been enhanced with fuzzy logic to ensure adaptability, and further improved with an ANFIS-based approach to combine fuzzy logic and artificial neural networks. Performance evaluation involves metrics utilizing speed and torque errors to gauge controller effectiveness. Comparing the fixed RF estimator to the ANFIS-tuned RF estimator with manually tuned speed PI, there is a performance improvement of 72.73%, 72.749%, and 46.636% for ISE, ITSE, and ITAE, respectively.

2024

This paper present the concept of improving harmonic distortion in power systems. Investigations were carried out for studying the effect of range dependent voltage switching and random voltage switching (sudden changes) in the input line voltage on the harmonic distortion at the output of the system. The analysis of the results showed that the insulated gate bipolar transistor (IGBT) based power system using the concept of switching resistor is capable of reducing harmonic distortion on the input power lines introduced because of external or internal load conditions. Harmonic distortions in the input and output of the conventional systems are estimated and compared. Reduction in the total harmonic distortion (THD) was also investigated for the proposed IGBT based power system. Keywords—Harmonic; IGBT; total harmonic distortion; dsPICmicrocontroller; signal processing technique; power system.

2024, Asian Journal of Control

This paper offers a straightforward analysis of a one-bit noise-shaping quantizer based on variable structure control methods. The method uses the concept of equivalent control to access the bound on the state signals when the sliding condition is reached. For a stable loop filter, the global stability can be proved to exist by using the Lyanpunov stability theory. For an unstable loop filter, this paper proposes a state constraint approach to ensure that the sliding condition is achieved. Simulation examples and an experimental circuit constructed using off-the-shelf electronic components are given to demonstrate the correctness of the theoretical analysis.

2024, Communications of The ACM

Large projection displays and video walls are already common in public spaces such as shopping malls and airports. As the enabling technologies continue to advance and decrease in price, these devices will become even more popular. At the moment, however, such displays are mainly noninteractive, and merely play uninterrupted video streams. When they are made responsive, however, they open up entirely new types of group interactions, in contrast with video kiosks, their smaller, presently ubiquitous cousins that deal mainly with single users. User interaction with large displays is a topic of considerable interest in the CHI and ubiquitous computing communities [1,2,3], where current research is exploring ways in which the user interface is distributed between various portals (e.g., handhelds, mobile and wearable devices, and large interactive surfaces) in responsive environments and augmented rooms. Many applications have been explored in professional niches like electronic blackboards for presentation, audiovisual portals for teleconferencing, augmented business and office environments, large electronic bulletin boards in corporate "water cooler" settings, interactive visualizations for design studios, and big-board displays for military and situation rooms. In contrast, the majority of the implementations introduced in this article are directed at public settings, where they are used for casual information browsing, interactive retail, and artistic installations or entertainment. Because their activity tends to be highly visible, participants at public interactive walls often become performers. These systems are intrinsically collaborativecrowds tend to gather around to watch, participate, and suggest choices as a user interacts with a large display; essentially all applications attain a social, gamelike quality. Although there are several products available that identify and track objects accurately across large electronic whiteboards and tablets, in order to be usable in public settings, it is important that such interactive walls respond to bare hands and do not require the user to wear any kind of active or passive target. At the moment, there are several sensing and tracking approaches that have been used to make large surfaces barehand interactive, many of which are introduced in [4]. The majority of these (e.g., capacitive sensing, resistive sandwiches, light curtains, active acoustics) are derived from touch screen technology [5]; while others are based on video tracking [6]. Most do not scale well to very large surfaces, however, or involve significant complication and robustness issues, especially in unstructured public or outdoor installations. The Responsive Environments Group at the MIT Media Lab has developed several relatively simple techniques to track activity across large surfaces [4]. All are essentially retrofits, as they do not require the installation of custom-designed material or any significant infrastructure. The first of these projects, the Gesture Wall, was an interactive music installation designed in 1996 for the Brain Opera [7], a large touring interactive media production currently installed at the Haus der Musik museum

2024, Proceedings of IEEE Sensors

We describe a system that locates the position of knocks and taps atop a large sheet of glass. Our current setup uses four contact piezoelectric pickups located near the sheet's corners to record the acoustic wavefront coming from the impacts. A digital signal processor extracts relevant characteristics from these signals, such as amplitudes, frequency components, and differential timings, which are used to estimate the location of the hit and provide other parameters, including the rough position resolution, the nature of each hit (e.g., knuckle knock, metal tap, or fist bang), and the strike intensity. As this system requires only simple hardware, it needs no special adaptation of the glass pane, and allows all transducers to be mounted on the inner surface, hence it is quite easy to deploy as a retrofit to existing windows. This opens many applications, such as an interactive storefront, with content controlled by knocks on the display window.

2024, ACM SIGGRAPH 2002 conference abstracts and applications

2024, International journal of programming languages and applications

In programmers point of view, Datatypes in programming language level have a simple description but inside hardware, huge machine codes are responsible to describe type features. Datatype architecture design is a novel approach to match programming features along with hardware design. In this paper a novel Data type-Based Code Reducer (TYPELINE) architecture is proposed and implemented according to significant data types (SDT) of programming languages. TYPELINE uses TEUs for processing various SDT operations. This architecture design leads to reducing the number of machine codes, and increases execution speed, and also improves some parallelism level. This is because this architecture supports some operation for the execution of Abstract Data Types in parallel. Also it ensures to maintain data type features and entire application level specifications using the proposed type conversion unit. This framework includes compiler level identifying execution modes and memory management unit for decreasing object read/write in heap memory by ISA support. This energy-efficient architecture is completely compatible with object oriented programming languages and in combination mode it can process complex C++ data structures with respect to parallel TYPELINE architecture support.

2024, IEEE Transactions on Industrial Electronics

In this paper, a DC-link structure feasible for integration with the circumscribing polygon modular integrated drives is proposed. The proposed DC-link structure combines both the DC-link capacitors and the busbar together and integrates them with the machine and the converter modules without increasing the outer diameter of the integrated machine/converter structure. A generic design methodology for the proposed DC-link structure is provided and applied on a reconfigurable fifteen stator coils concentrated winding axial flux machine for all its possible phase configurations. The design methodology presented in this paper involves the determination of the required DC-link capacitance and the multi-physics design of the bus-bar. The parasitics of the bus-bar part of the proposed DC-link structure are evaluated using electromagnetic FEM models and their influence on the DC-link waveforms is evaluated. Due to the expected high ambient temperature inside an integrated drive, electromagnetic and CFD models are developed for the proposed DC-link structure to evaluate the loss density and the temperature distribution of the bus-bar to ensure reliable operation. An experimental setup is built to validate the design methodology. Index Terms-Integrated modular drives, DC link capacitors, DC link bus-bar, Wide Bandgap converters, Parasitic inductance, Bus-bar thermal modelling, Bus-bar electromagnetic modelling, DC-link voltage spike. Manuscript received Month xx, 2xxx; revised Month xx, xxxx; accepted Month x, xxxx. This research is part of the ModulAr SBO project funded and supported by Flanders Make vzw, the strategic research centre for the manufacturing industry.

2024, IEEE Transactions on Computers

Continuous advances in silicon technology enable the development of complex System-on-Chip as cooperation among Digital Signal Processors (DPSs), General Purpose Processors (GPPs), and specific hardware components. The impact of this choice is not only limited to the target architecture, but also encompasses the overall system specification. It is thus crucial to manage such a complexity using high-level specification languages and a tool chain supporting the designer throughout a set of strategic decisions, such as the identification of a set of possible target architectures, the verification of the correctness of the specification, and the partitioning of the specification onto a set of computational resources. This paper addresses this type of problem by proposing a design flow supporting the system-level design of heterogeneous multiprocessor system-on-chip (MP-SoC), by extracting information from the system description (e.g., SystemC)-statically and in a fast manner-and by providing a set of quantitative measures correlating the type of executor, the functionality, and a timing estimation. Partitioning and architecture selection are built on top of this data and the final analysis of the selected Hardware-Software solution over the identified candidates is finally submitted to a timing verification via simulation. Note that the possibility of actually performing a comprehensive design space exploration, in general, is tightly influenced by the interaction between partitioning/architecture-selection and timing simulation in the design flow; for this reason, the description of this aspect is particularly emphasized in the presentation of the methodology. To show the applicability of the proposed methodology, two relevant case studies are described in the paper.

2024, IEEE CCECE2002. Canadian Conference on Electrical and Computer Engineering. Conference Proceedings (Cat. No.02CH37373)

In this paper, we describe formal modelling of the digital signal processors of the family ADSP-2100 using the HOL (Higher Order Logic) theorem prover. While specifying the behavior and implementation of the processor, we solved the problem of complexity related to the large number of parameters by using a structured method based on our knowledge about the processor architecture. We show details of the specification strategy used and display few illustrative examples.

2024, IEEE Transactions on Vehicular Technology

Significant improvements in terms of reduced power consumption and increased bandwidth are obtained if a digital predistortion linearizer is implemented with an application specific digital signal processor. This paper investigates the quantization effects in different parts of a table based complex gain predistortion linearizer. The analysis can be used to optimize the predistortion linearizer with respect to wordlength based on the knowledge of the RF amplifier gain characteristic, the probability density function for the modulation scheme and the maximum allowable adjacent channel interference level. A predistorter chip is described that has been designed using the analysis. The chip has been fabricated and tested. Compared with a standard digital signal processing (DSP) solution it provides seven times higher bandwidth but consumes only 10% of the power.

2024, Sensors, MDPI AG Vol. 24: No. 9. pp. 2732

In the modern technological era of sophisticated applications and high-quality communications, a platform of clever strategy and quickly updated systems is needed. It should be capable of withstanding the fastest emerging problems like signal attenuation and hostile actions intended to harm the whole network. The main contributions of this work are the production of an OFDM system (with low cost) that can sustain high-speed communications and be easily adjusted with new integrated code while exhibiting the feasibility of implementing a transmitter–receiver system in the same DSP and demonstrating the holistic approach with the qualitative integration of such an architecture in a warfare scenario. Specifically, in this research, the point of view is toward three facts. The first is to show a method of quick self-checking the operational status of a digital signal processor (DSP) platform and then the pedagogical issues of how to fast check and implement an updated code inside DSPs through simple schematics. The second point is to present the prototype system that can easily be programmed using a graphical user interface (GUI) and can change its properties (such as the transmitted modulated sinusoids—orthogonal frequency division multiplexing subcarriers). Alongside the presentation, the measurements are presented and discussed. These were acquired with the use of an oscilloscope and spectrum analyzer. The third point is to qualitatively show the application of such a system inside a modern warfare environment and to recommend various potential system responses according to the development of such a platform of reconfigurable implemented OFDM systems. The implementation was performed for two types of systems: (1) transmitter and (2) transmitter–receiver system. Notably, the system acts quickly with a delay of about 1 msec in the case of transmitting and receiving in the same DSP, suggesting excellent future results under real conditions.

2024, Canadian Acoustics

This paper will present the feasibility o f utilizing a miniaturized, real-time, in-ear, digital signal processing devices to investigate experience-dependent brain plasticity in the humans. An important component of this trial is the use of a recently developed digital hearing protector (from Sonomax, Montreal, QC) made with a custom earpiece that is instantly fitted to the user's ear, tested for attenuation and then equipped with a miniaturized set o f microphone, receiver and Digital Signal Processor. The D S Pis a versatile audio platform, originally designed for hearing aid applications, but that has also been successfully programmed for several other applications like a non-linear earplug (offering more attenuation when the ambient noise is higher) and as a musician's earplug (offering a constant attenuation over a wide frequency range together with a loudness correction). The central idea of the current study is to use such digital earplugs to change a person's sound perception, in real-time, in-and outside o f the laboratory. Various time and frequency manipulations will be performed on the signal pickup by the microphone and transmitted to the subject's ear by the receiver, while monitoring the brain plasticity with neuroimaging techniques. Preliminary results using a notch filter demonstrate tonotopic reorganization following sensory modification in the human auditory cortex.

2024

2024, 32nd Design Automation Conference

We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conventional code generation methods typically result in inefficient code. In this paper we formulate and solve some optimization problems that arise in code generation for processors with irregular datapaths. In addition to instruction scheduling and register allocation, we also formulate the accumulator spilling and mode selection problems that arise in DSP microprocessors. We present optimal and heuristic algorithms that determine an instruction schedule simultaneously optimizing accumulator spilling and mode selection. Experimental results are presented.

2024, IEEE/ACM Transactions on Audio, Speech, and Language Processing

Wave Field Synthesis (WFS) is a multichannel audio reproduction method, of a considerable computational cost that renders an accurate spatial sound field using a large number of loudspeakers to emulate virtual sound sources. The moving of sound source locations can be improved by using fractional delay filters, and room reflections can be compensated by using an inverse filter bank that corrects the room effects at selected points within the listening area. However, both the fractional delay filters and the room compensation filters further increase the computational requirements of the WFS system. This paper analyzes the performance of a WFS system composed of 96 loudspeakers which integrates both strategies. In order to deal with the large computational complexity, we explore the use of a graphics processing unit (GPU) as a massive signal co-processor to increase the capabilities of the WFS system. The performance of the method as well as the benefits of the GPU acceleration are demonstrated by considering different sizes of room compensation filters and fractional delay filters of order 9. The results show that a 96-speaker WFS system that is efficiently implemented on a state-of-art GPU can

2024, IEEE Transactions on Nuclear Science

2024, International Journal of Renewable Energy Research

This paper presents a dual-axis solar tracker based on a real-time measurement of solar radiation. For this, Matlab-Simulink was used to perform the dynamic model of: solar radiation, electromechanical system and solar panel. The implementation of the solar tracker was performed using a digital controller that processes signals from radiation sensors and inertial measurement unit. The acquired data are contrasted with a mathematical algorithm to calculate sun’s position and set the control action to orient the panel. A real-time processing system with internal memory capacity was developed, which considers the relative position between the radiation sensor and solar panel to improve system efficiency. The obtained simulation results confirm the approach robustness. Preliminary results with the solar tracker show a maximum increase of 9.87% in the energy obtained from dual-axis solar panel compared with energy from a fixed panel optimally oriented. The tests were performed using two ...

2024

Plane-wave decomposition by sparse recovery is a reliable and accurate technique for plane-wave decomposition which can be used for source localization, beamforming, etc. In this work, we introduce techniques to accelerate the planewave decomposition by sparse recovery. The method consists of two main algorithms which are spherical Fourier transformation (SFT) and sparse recovery. Comparing the two algorithms, the sparse recovery is the most computationally intensive. We implement the SFT on an FPGA and the sparse recovery on a multithreaded computing platform. Then the multithreaded computing platform could be fully utilized for the sparse recovery. On the other hand, implementing the SFT on an FPGA helps to flexibly integrate the microphones and improve the portability of the microphone array. For implementing the SFT on an FPGA, we develop a scalable FPGA design model that enables the quick design of the SFT architecture on FPGAs. The model considers the number of microphones, th...

2024, IOSR Journal of Mechanical and Civil Engineering

The output of a solar panel depends on various factors and one of them is the tilt angle of the panel. Though small changes in the tilt angle might not cause great difference in the output of a panel but when we talk about huge solar photovoltaic plants, even a small difference in solar tilt may result in loss of hundreds of kilowatt. This paper focuses on optimizing the tilt angle for fixed support panels at VIT University (Vellore, India). The paper lays more focus on weighted average calculation of tilt angle rather than calculation of simple average. The graphical and analytical calculations as well as Simulink analysis gives an accurate tilt angle of 19.5640 o instead of 17.7093 o which is found by simple averaging method in MATLAB. Though this 2 degrees difference would not matter for small plants but for plants with more than 5 MW capacity, this optimization of 2 degrees can help save a lot of energy.

2024, 3RD INTERNATIONAL SCIENTIFIC CONFERENCE OF ALKAFEEL UNIVERSITY (ISCKU 2021)

2024

Digital filters play a major role in Very Large-Scale Integration Technology (VLSI), as most VLSI systems use addition as an integral operation. One such filter is FIR filter, whose basic implementation is achieved by adders. This paper mainly aims at designing a Moving Average 4-tap FIR filter using Verilog HDL and is implemented using Xilinx software and Spartan 6 FPGA kit with the concepts of Multiply and Accumulate (MAC) operation and convolution.

2024, Advanced Research in Electrical and Electronic Engineering

This paper present the design of DSP standalone evaluation board and implementation of DSP based algorithm to generate SPWM signal, used to drive the gate driver of IGBT. The preferred method of controlling the heat inside Induction Heating Systems, is to vary the frequency of the AC voltage driving the Induction Heating Systems. The DSP provides variable frequency (PWM) signal that controls the applied voltage on the gate driver, which provides the required PWM frequency with less harmonics at the output of the power inverter. The algorithm development methodology and the experimental results are presented.

2024, Tm-technisches Messen

In this paper, the author seeks to perform an online measurement of the electrodes impedances in an electromagnetic flowmeter that could be covered by coatings or not. This online measurement of the electrode impedances determine the magnitude and phase of impedance changes during the operation of the flowmeter. This means that it is possible to assess the accuracy of lumped element models for the measuring cell of the flowmeter. In addition, these measurements are useful to determine the lower frequency limit above which the reading of the induced voltage level of the electromagnetic flowmeter can be carried out with a sufficient signalto-noise ratio and are useful as well to determine the required input impedance of the preamplifier in the working frequency range.

2024, Iete Journal of Research

This paper presents a digital implementation of a new and simple control technique for single-phase Hybrid Active Power Filter (HAPF). The main control consists of an accurate estimation technique used to extract harmonic current generated by nonlinear loads. The estimation of harmonic current is done by using multiple units of an Adaptive Notch Filter (ANF) linked together in parallel structure; each unit is used to estimate a specified harmonic component. The frequency estimation is then carried out based on the output of these units. Therefore, the sum of these harmonic components will be the reference signal for the active power filter to generate the appropriate compensation signal. A laboratory prototype model of the HAPF was developed and its control strategy was implemented digitally in TMS320F2808. The theoretical expectations were verified and demonstrated experimentally.

2024

This paper presents an effective technique for harmonic current mitigation using an adaptive notch filter (ANF) to estimate current harmonics. The proposed filter consists of multiple units of ANF connected in parallel structure; each unit is governed by two ordinary differential equations. The frequency estimation is carried out based on the output of these units. The simulation and experimental results show the ability of the proposed tracking scheme to accurately estimate harmonics. The proposed filter was implemented digitally in TMS320F2808 and used in the control of hybrid active power filter (HAPF). The theoretical expectations are verified and demonstrated experimentally.

2024, IEEE Transactions on Instrumentation and Measurement

2024, 2010 IEEE 8th Symposium on Application Specific Processors (SASP)

The correlation process in direct sequence spread spectrum (DSSS) communication systems is key in having successful signal reception. The implementation of real-time correlation in digital signal processors is one of key challenge in the realization of positioning systems today; as a result, most realizations are either application specific integrated circuits (ASIC) or Field Programmable Gate Array (FPGA) based. In this work we have introduced a new correlation engine targeting performance critical Global Positioning Satellite (GPS) based positioning. The processor is based on Reconfigurable Instruction Cell Array (RICA) paradigm. The GPS has been chosen due to its extensive integration in handheld devices (e.g. mobile phones) together with rising energy consumption concerns. We have designed, programmed and implemented several time-domain correlator engines based on RICA architectural paradigm. Various optimization techniques were implemented to adapt the processor to the correlation algorithm and in order to achieve the best performance. 12 and 24 channel correlators are tested using the new processor architecture.

2024, IEEE Transactions on Instrumentation and Measurement

The external and internal algorithmic specification of an application-specific digital signal processor (ASDSP) under development, dedicated to spectrometric applications, is presented. The processor is intended to perform the correction of spectrometric data subject to errors of diversified origins, using sophisticated digital-signal-processing algorithms. The set of algorithms to be implemented in the processor is proposed. Its suitability for implementation in an application-specific integrated circuit is demonstrated by functional design of the corresponding processor.

2024, Proceedings of the Sixth International Symposium on Signal Processing and its Applications (Cat.No.01EX467)

This paper describes the implementation of the Wavelet Codec (Encoder and Decoder) by using the Texas Instruments DSP (Digital Signal Processor) TMS320C6701 on the EVM (Evaluation Module) Board. The Wavelet Codec is used te compress and decompress gray scale image for real time data compression. The Wavelet Codec algorithm has been transferred into C and assembly code in Code Composer Studio in order to program the 'C6xx DSP processor. The capability of the 'C6xx to change the code easily, correct or update applications, reducing the development time, cost and power consumption. With the development tools provided for the 'C6xx DSP platform, it created easy-to-use environment that optimizes the devices' performance and minimizes technical barriers to software and hardware design.

2024, 18th International Conference on Electronics, Communications and Computers (conielecomp 2008)

In this work we present the analysis and implementation in a digital signal processor (DSP), of a variant of the Least Mean Square (LMS) algorithm. Modification is based on codifying the error of the algorithm, in order to reduce the design complexity for its implementation in digital adaptive filters, because the error is made up of whole values. The results demonstrate an increase in the convergence speed; it's affected indirectly by the convergence factor, and to obtain a floating point operation reduction, which accelerates processing. These, to demonstrate the results obtained from the implementation of the algorithm in the digital signal processor TMS320C6713 by Texas Instruments.

2024, IEEE Transactions on Instrumentation and Measurement

Performing accurate average current drain measurements of digital programmable components (e.g., microcontrollers, digital signal processors, System-on-Chip, or wireless modules) is a critical and error-prone measurement problem for embedded system manufacturers due to the impulsive timevarying behavior of the current waveforms drawn from a battery in real operating conditions. In this paper, the uncertainty contributions affecting the average current measurements when using a simple and inexpensive digital multimeter are analyzed in depth. Also, a criterion to keep the standard measurement uncertainty below a given threshold is provided. The theoretical analysis is validated by means of meaningful experimental results.

2024, Archives of Electrical Engineering

This paper describes a three phase shunt active power filter with selective harmonics elimination. The control algorithm is based on a digital filter bank. The moving Discrete Fourier Transformation is used as an analysis filter bank. The correctness of the algorithm has been verified by simulation and experimental research. The paper includes exemplary results of current waveforms and their spectra from a three phase active power filter.

2024, IEEE Transactions on Energy Conversion

2024, Jurnal Infotel

In general active sun trackers move because they respond to light sensors that measure the intensity of sunlight. However, sensor-based trackers are usually more expensive than sensor-less trackers. In addition, based on several studies, a comparison between the sensor and sensorless based tracker only reports lower tracking error and higher power generation for sensor-based than sensorless tracker. However, it does not include an analysis of energy use on the sensor. Therefore, this study aims to design a sensorless closed-loop tracking system for solar panels with two degrees of freedom. The tracking controller in this study is based on the Fuzzy Logic Controller (FLC) method. In this study, a dual-axis PV can increase power output by 20.2% compared to a fixed PV (0 ° axis position). In comparison to a fixed PV, dual-axis PV adjusts the solar panel perpendicular to the sun's position to optimize electrical conversion.

2023, Zbornik radova pisanih za 5. Međunarodnu konferenciju o obnovljivim izvorima električne energije

U ovom radu je predstavljena edukativna laboratorijska postavka upravljanja motorom jednosmerne struje u realnom vremenu baziranog na dSPACE1104 platformi. Laboratorijska postavka omogućava sagledavanje principa upravljanja motorom jednosmerne struje i određivanja parametara regulacionih petlјi struje i brzine motora. U radu je najpre detalјno opisan korišćeni hardver (digitalni kontroler, energetski pretvarač i neophodne kartice za izolaciju i prilagođenje signala) a potom softverski model upravlјačke strukture izrađen u MATLAB/Simulinku. dSPACE kontroler povezan je sa realizovanim Simulink modelom što omogućava jednostavno i brzo generisanje upravljačke aplikacije (eng. rapid control prototyping), odnosno interakciju simulacije sa realnim upravljačkim sistemom. Takođe, na ovaj način omogućeno je jednostavno podešavanje parametara regulatora struje i brzine kao i praćenje odziva regulisanih veličina. Ovaj rad naglašava edukativni aspekt realizovane laboratorijske postavke upravljanja motorom jednosmerne struje. Potrebne vrednosti pojačanja regulatora struje i brzine dobijene su matematičkom analizom modela upravljanja a potom su simulacioni rezultati upoređeni sa rezultatima dobijenim eksperimentalnim putem na realnom sistemu. Na ovaj način studentima koji pohađaju kurs Regulacija elektromotornih pogona je omogućeno da bolje razumeju princip rada savremenih digitalnih kontrolera u pogonu motora jednosmerne struje. Realizovana laboratorijska postavka otvara mogućnost za analizu energetske efikasnosti elektromotornog pogona u zavisnosti od načina upravljanja odnosno primene različitih upravljačkih algoritma brzom izradom prototipa.

2023, IET Electric Power Applications

A new generated pulse width modulation (PWM) technique is presented, making it possible to significantly reduce harmonics in comparison to currently used PWMs operating in real time. This improvement means that a motor connected to an inverter that is controlled with this technique undergoes less overheating and vibrations, thereby improving its performance.