Field Programmable Analog Array Research Papers (original) (raw)

2025, Microelectronics Journal

This paper proposes a self-test strategy, analog configurability test (ACT), for an embedded analog configurable circuit (EACC) composed of operational amplifiers and interconnection resources that are present in the MSP430 microcontroller family from Texas Instruments s . The ACT strategy minimizes the cost in hardware overhead by employing only the hardware and software resources of the microcontroller. Our test proposal consists in programming a reduced set of available configurations for the EACC and testing its functionality by measuring only a few key parameters. The processor executes an embedded test routine that sequentially programs the configurations, acquires data from an ADC channel and performs required calculations. The test strategy is experimentally evaluated using a commercial hardware provided by the vendor. Our experimental results show very good repeatability, with errors below the expected.

2025, Microelectronics Journal

2025, Journal of Low Power Electronics and Applications

We present a novel remote test system, an integrated remote testing system requiring minimal technology support overhead, enabled by configurable analog-digital Integrated Circuits (IC) to create a simple interface for a wide range of experiments. Our remote test system requires no additional setup, resulting both from using highly configurable devices, as well as from the advancement of straight-forward digital interfaces (i.e., USB) for the resulting experimental system. The system overhead requirements require simple email handling, available over almost all network systems with no additional requirements. The system is empowered through large-scale Field Programmable Analog Array (FPAA) devices and Baseline Tool Framework (BTF), where we present a range of experimentally measured examples illustrating the range of user interfacing available for the remote user.

2025, Journal of Low Power Electronics and Applications

2025, Lecture Notes in Computer Science

This paper presents novel pulse based techniques initially intended to implement signal processing functions such as analogue and mixed-signal filters, data converters and amplitude modulators. Field programmable devices using these techniques have been implemented and used on a demonstration board to implement analogue and mixedsignal arrays. The rich mix of analogue and digital functionality provided by Palmo systems combined with the fact that they may accept random configuration bit streams makes them most attractive as platforms for evolvable hardware.

2025, Lecture Notes in Computer Science

2025, Universidade Federal Rural do Semi-Árido

© Todos os direitos estão reservados a Universidade Federal Rural do Semi-Árido. O conteúdo desta obra é de inteira responsabilidade do (a) autor (a), sendo o mesmo, passível de sanções administrativas ou penais, caso sejam infringidas as leis que regulamentam a Propriedade Intelectual, respectivamente, Patentes: Lei n° 9.279/1996 e Direitos Autorais: Lei n°9 .610/1998. O conteúdo desta obra tomar-se-á de domínio público após a data de defesa e homologação da sua respectiva ata. A mesma poderá servir de base literária para novas pesquisas, desde que a obra e seu (a) respectivo (a) autor (a) sejam devidamente citados e mencionados os seus créditos bibliográficos.

2025

Field Programmable Analog Array (FPAA) are reconfigurable analog modules introduced on the electronic market in the last decade. Their working and, in particular, their programmability is achieved owing to the use of switched capacitors technology. At least in principle, they seem to be a very attractive and powerful tool to design analog circuits whose parameters have to be tuned to signal variations as in carrying out sensor conditioning systems. But, the aim of exploiting their possibilities in the field of metrology requires a complete characterization and performance assessment of the involved building blocks. With this goal, in the paper, the metrological characterization of the most commonly blocks to be used in analog conditioning circuits, such as amplifiers and filters, is performed. These blocks have been characterized in terms of both frequency response and step response and the obtained experimental results have been compared with the ones expected from theoretic analys...

2025, Measurement

Tests of field programmable analog arrays (FPAA) are required to assess tolerance to variations of components, due to aging, uncertainty, or external disturbances. The paper focuses on radiated electromagnetic energy as a cause for a possible faulty behavior: results show that input and output channels of the FPAA are affected by the presence of noise due to the coupling of the incident field with the board, and that the susceptibility profile depends on the configuration of the FPAA and the field's polarization. Therefore, topology and electromagnetic characteristics of the board must be carefully designed. Moreover, the transfer function is susceptible to the incident field to a degree that depends on the configuration of the FPAA and the field's amplitude and frequency. This limits application of FPAAs in critical applications like in the automotive and aerospace industry, where fields with large amplitudes are likely to be encountered during normal operation.

2025, Proceedings of the IEEE

Many animals rely on visual motion to infer their relation to the surrounding environment while moving around in it. Motion processing in biological nervous systems, particularly in the insects, has been a subject of active research for over 50 years. With the advent of interest in ''neuromorphic'' integrated circuits in the late 1980s, this mode of sensory processing has also been the subject of various analog silicon modeling efforts. The author discusses the background of certain models for motion detection in insects, and then the implementation of a particular model in analog integrated circuitry. The paper does not focus on such circuits themselves, however, but on the issue of computational precision in the analog domain: it is argued that insufficient attention to this issue has been an impediment to the development of neuromorphic circuits that are practically useful in engineering applications. A statistical approach is described for assessing one of the designs discussed herein, and the degradation of its performance due to variations in the electrical properties of its constituent devices, with an eye toward suitability for application in autonomous robotics. This approach relies on tools and models routinely used in conventional analog/mixed signal design. The author argues that adoption of such techniques, along with a deeper consideration of computational precision, i.e., a shift in the neuromorphic design philosophy, would be an important step in moving the field forward.

2025, NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.

This paper presents experimental results of fast intrinsic evolutionary design and evolutionary fault recovery of a 4-bit Digital to Analog Converter PAC) using the JPL stand-alone board-level evolvable system (SABLES). SABLES is part of an elport to achieve integrated evolvable systems and provides autonomous, fast (tens to hundreds of seconak), on-chp evolution involving about 100.000 circuit evaluations. Its main components are a JPL Field Programmable Tronsistor Array (FPTA) chip used ar transistor-level recontgurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper describes an experiment consisting of the hierarchical evolution of a 4-bit DAC using 20 cells of the FPTA chip. Fault-recovery is demonstrated aper applying stuck-at 0 faults to all switches of one particular cell, and using evolution to recoverfunctionality. It has been veri$ed that thefunctionality can be recovered in less than one minute aBer the fmlt is detected while the evolutionary design of the 4-bit DACfrom scratch took about 3 minutes. ' lLSB =Vrefl16, forVref=453mV.

2025, Springer eBooks

The design of a high-frequency ®eld-programmable analog array (FPAA) is presented. The FPAA is based on a regular pattern of cells interconnected locally for high frequency performance. No switches of any kind are used in the signal path of a cell: programming of the functions, parameters, and interconnections is achieved solely by modifying cells' bias conditions digitally. Limited global signal interconnections are also available for those application circuits which cannot be mapped onto locally-only interconnected structure. Key circuits of the FPAA have been fabricated in a CPI transistor-array bipolar technology.

2025, International Journal of Computer Applications

The current mode programmable analog modules are realized using digitally controlled low voltage CMOS current conveyors. These programmable modules include current mode amplifiers, integrators, differentiators, first order multifunctional filter and second order multifunctional filters. The realized current mode programmable analog modules can provide digital control to the parameters through an n-bit control word with high resolution capability and reconfigurability. These programmable analog modules are suitable for realizing current mode field programmable analog array. The realized programmable analog modules are designed and verified using PSPICE and the results thus obtained justify the theory.

2025, 2008 American Control Conference

For topography measurements and faster imaging with the AFM a high control-bandwidth is required. This paper presents an analog implementation of a model-based controller for a high-speed Atomic Force Microscope (AFM) using a new type of control hardware. The vertical positioning axis of the AFM scanner is modeled, and the imaging bandwidth is improved by means of model-based control. The new feedback controller, which is designed in the H∞-framework, is implemented on a Field Programmable Analog Array (FPAA), which enables operation of the model-based controlled AFM system at a feedback bandwidth on the order of 100 kHz. Measured results demonstrate that the closed-loop system recovers from a step-like disturbance within 7 microseconds. Recorded AFM images verify a significant performance improvement of the model-based controlled system over the analog proportional-integral (PI) controlled AFM.

2024, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware

Reconfigurable chips are integrated circuits whose internal connections can be programmed by the user to attend a specific application. Field Programmable Gate Arrays (FPGAs) and Field Programmable Analog Arrays (FPAAs) constitute the state of the art in the technology of reconfigurable chips, referring to digital and analog devices respectively. These devices will become the building blocks of a forthcoming class of hardware, with the important features of self-adaptation and selfrepairing, through automatic reconfiguration. These are essential features for systems that need to perform for a long time in harsh environments such as those employed in space exploration missions. Automatic reconfiguration of field programmable devices may potentially be driven by Evolutionary Computation techniques such as Genetic Algorithms. FPAAs have just recently appeared, and most projects are being carried out in universities and research centers. In this article we propose a new model of reconfigurable analog circuit and describe its application in the intrinsic evolution of a simple logic inverter .

2024, 27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004.

The goal of evaluation platforms is design time and verification costs reduction, as these are the main parameters affecting time to market and final success of a product. Following article describes a new approach to prototyping of complex mixed-signal systems, suitable especially as a platform for system developers. Both, digital and analog subsystems can be emulated within one development kit. Digital part is based on the ARM ASIC-Integrator Kit, targeting rapid development of embedded applications. Patented Electrically Programmable Analog Array (EPAA) acts as the part morphing the functionality of the analog subsystem. EPAA with fully parametrizable architecture allows either for transistor-level design of various analog function blocks, or reuse of pre-designed macros. In-field parameter adjustment and topology configuration designates the EPAA to be used in sensor and actor technology, or signal conditioning. Dedicated configuration software has been developed, allowing for various modi of device configuration, depending on the designer's experience and used abstraction level.

2024

Encouraged by the recent progress in the FPAA technology, we propose a flexible membership functions synthesis method based on the configurable filter blocks. Based on the actual paradigm of FPAA we consider an interesting and promising idea to implement the membership functions using the frequency-response curves of the analog filters. The other specific functional blocks can be implemented with programmable analog structures obtaining a complete unit for fuzzy inference processing.

2024

I n this paper we propose a novel approach to the realization of continuous, fiuzy, and multi-valued logic (mvl) circuits. We demonstrate how a general-purpose field programmable analog array (FPAA), with cells realizing simple arithmetic operations on signals, can be used for this purpose. The FPAA, which is being implemented in a bipolar transistor array technology, operates from f3.3V or f s V power supplies and works in the range of frequencies up to several hundred MHz.

2024, 2011 XXXth URSI General Assembly and Scientific Symposium

A novel concept for RFID tag localization using a tunable near-field focused circular-phase array antenna working at 5.8 GHz is presented. It serves as the reader antenna and focuses the power into a small region, in the tag vicinity. By scanning the focal spot along one axis and monitoring the differential scattered power by a tag, its position along the axis is easily computed with good accuracy. This simple localization scheme is well adapted for specific localization scheme, for example for objects placed over a conveyor belt.

2024

This paper presents an eighth order low-pass filter which has characteristics of fault tolerance through the use of evolvable hardware (EHW). A field programmable analog array (FPAA) is used to implement the filter under study. The reconfiguration process of the filter involves the execution of a genetic algorithm (GA) in an external computer, after a fault is detected. To perform the test of the filter, we assume that a frequency response characterization test is used. A parametric fault model that considers deviations in the values of one of the capacitors or one of the input amplifiers (IA) is used to evaluate the performance of developed GA. The results show that GA finds filter configurations that meet the restrictions set for all the simulated faults. Additionally, this work shows better results compared to those previously obtained using another EHW scheme for the same low-pass filter.

2024, IEEE Journal of Solid-State Circuits

A field-programmable analog array (FPAA) using a standard-CMOS wide-dynamic-range translinear element (TE) is introduced. The FPAA configurable analog blocks (CABs) are based on a reconfigurable translinear cell (RTC), capable of implementing the basic circuit elements required by translinear and log-domain circuit design. The interfacing is provided by an I/O programmable cell, which allows for easier connectivity between the signal-processing core and the external circuitry. As a proof-of-concept, a 5 5 RTC FPAA testchip was implemented in 0.35-m CMOS technology. A set of various circuit primitives, such as one-and four-quadrant multipliers, an Euclidean distance operator and a fourth-order log-domain filter, were mapped on the chip in order to demonstrate the versatility of the approach. FPAA bandwidth reaches 20 MHz with a power consumption of 30 W/TE and precision errors below 3%.

2024, ECTI Transactions on Electrical Engineering, Electronics, and Communications

This paper presents a pulse response-based builtin self test technique and implementation for the testing of analog integrated circuits in mixed-signal systems. This BIST technique employs two narrow width pulses as input stimuli, and monitors two voltage samples on pulse response waveform for fault detection through allowable tolerances. The BIST system implementation realizes a programmable delay line for generating pulse stimuli, and a sample-and-hold circuit with comparators for fault detection process. Demonstrations of the testing for a Sallen-Keylow-pass ¯lter using 0.18-?m CMOS technology yields relatively high fault coverage. The fault coverage of catastrophic faults is 100%, and the fault coverage of capacitor and resistor variations are 93.75% and 87.5%, respectively. The proposed BIST technique uses low testing time within two short pulse response waveforms, and o®ers low implementation cost since onchip sinusoidal stimuli, test algorithms, and external digital processin...

2024, HAL (Le Centre pour la Communication Scientifique Directe)

The design of checkers aimed at the concurrent test of analog and mixed-signal circuits is considered in this paper. These checkers can on-line test duplicated and fully differential analog circuits. The test approach is based on exploiting the inherent redundancy of these circuits which results in the use of a code for the analog signals. The analog code is monitored by the checkers. An error signal which complies with existing digital self-checking parts is generated in the case that a code falls out of the valid code space. For the verification of the analog codes, absolute tolerance margins and tolerance margins which are made relative to signal amplitude are considered. A test pattem generator for off-line testing of the checkers is proposed.

2024

Os metodos de controle estao cada vez mais presentes no campo industrial, tal fato gera uma constante necessidade de inovacao sobre o tema. Este trabalho apresenta uma revisao sobre controladores PID de ordem fracionaria. Inicialmente e apresentada a historia do calculo fracionario e suas definicoes mais utilizadas em sistemas de controle. Posteriormente e realizada uma analise sobre diversos trabalhos envolvendo controladores PID de ordem fracionaria (FOPID), buscando mostrar o desempenho superior deste tipo de controlador em relacao ao PID convencional. Contudo, ainda sao necessarias pesquisas sobre o tema a fim de precisar com mais detalhes as caracteristicas de tais controladores.

2024

2024, Anais do SIMPROC

Este trabalho tem como objetivo apresentar uma sucinta comparação qualitativa, com base nos gráficos de resposta de sistema controlados a um degrau, entre um controlador de ordem inteira pelo método de Ziegler-Nichols e duas formas de sintonia de controle fracionário: o método de Valério e de Padula. A semelhança entre todas estas regras de sintonia é a de que todas trabalham com a função transferência de primeira ordem com atraso (FOPDT).

2024

Mixed-signal circuits are increasingly utilized in many applications, especially in communication systems. Analysis and design of such circuits is very complex. Software support tools for analysis, simulation, and design are in development. Availability of programmable analog and digital devices have brought the idea of construction a development board for mixed signal circuits. Such a board could be used for fast prototyping, experimental studies, verification of models etc. This article will explain the design of a mixed signal development board, its hardware and integrated software, carried out at the Center for Low Power Electronics at the University of Arizona in cooperation with Western Design Center (WDC). The major components used in the design are the Motorola's field programmable analog array (MPA020) and WDC microprocessor development board.

2024, Journal of Applied Sciences

2024, Advanced Materials Letters

2024, 2014 IEEE PES General Meeting | Conference & Exposition

2024, IFAC Proceedings Volumes

This paper examines how custom computing hardware for fast power system analysis may be adapted to improve the user experience as well as its commercial-viability. One prime example of such custom hardware is the FPAA-based analog emulator developed previously by the authors. The authors propose development of a USB-based actuation and data acquisition interface that allows analog computational tools to work seamlessly with one or more commercially-available power system analysis software packages. A commercially-available software application will be tasked with user interaction and post-processing, while custom hardware is tasked with faster-than real-time power system analysis.

2024, Proceedings of 2010 IEEE International Symposium on Circuits and Systems

This paper is an extension of the authors' previous works in the area of field programmable analog arrays (FPAA). It presents the design, construction, and testing of an FPAA-based hardware prototype to emulate the dynamic behavior of a basic power system generator. The programmable nature of the FPAA is key-significantly reducing the effort and time required to develop a working prototype and VLSI design.

2024

The paper presents training experiments in interfacing sensors to Field Programmable Analog Array (FPAA). To this aim the internal structure and operation of AN221E04 chip of Anadigm Inc. is investigated. Different examples for application of FPAA in sensor circuits are discussed. The results are applied in the design and verification of circuit for modeling of transfer characteristic of DC thermistor bridge. The presented approach will find wide application in education and research in electronics.

2024

O projeto PROCIMS envolve basicamente o desenvolvimento de uma matriz de transistores, a partir da especificação de sua célula básica, composta de transistores tipo n e p de geometrias diferentes, em tecnologia digital CMOS 1,0 um, para projeto de circuitos mistos-analógico-digitais. O projeto digital é realizado utilizando-se células lógicas previamente desenhadas e simuladas. Este conjunto de células recebe a denominação de biblioteca de células lógicas. O posicionamento destas células na matriz e seu roteamento ou interconexão deverá ser realizado com ferramentas de CAD desenvolvidas pelo GME-Grupo de Microeletrônica. Muitas destas ferramentas de projeto necessitarão de reprogramação para se adequarem à arquitetura da nova matriz de transistores proposta. Para o projeto analógico está previsto o desenho de blocos analógicos de uso geral como espelhos de correntes, amplificadores operacionais e comparadores de tensão. Diversos circuitos estão sendo implementados para validar esta metodologia, dentre os quais portas lógicas, flip-flops, somadores, células de memória e amplificadores operacionais. Neste momento, os resultados obtidos por simulação mostram que os circuitos desenhados, principalmente os analógicos, apresentam um bom desempenho.

2024, Proceedings of the 24th symposium on Integrated circuits and systems design

Este artigo se trata de uma aplicação com células extendidas únicas em uma única fase de tempo(E-TSPC) , em blocos de alta qualidade de circuitos digitais. O E-TSPC é uma técnica eficiente para aplicações em circuitos digitais. O resultado dessas simulações revelaram um aumento significativo de velocidade e aumento de desempenho cerca de 21% e 31% respectivamente, comparando a velocidade da implementação e redução de velocidade destes circuitos digitais, obteve-se 168% e 51%, respectivamente nas células implementadas. A técnica E-TSPC Esta técnica representa uma forma simples de representar blocos em seções separadas em circuitos digitais, complementando blocos estáticos e dinâmicos. Implementação em células Um bloco E-TSPC ordenado, implementa circuitos complexos. O design do circuito é similar ao desenvolvimento analógico dos próprios circuitos. Observe que a implementação dos blocos de circuitos é facilmente entendido através das funções implementadas nas portas negativas (Inversores) nos circuitos. Esta aplicação E-TSPC trouxe uma alta velocidade nos blocos de transmissão dentro dos circuitos. Pode-se comparar a implementações pré-escalares de 32/33 em aplicações de aproximação lógica total. As implementações E-TSPC revelaram uma velocidade de performance de incremento e força de 21% e 31% respectivamente. Os resultados facilitaram a adição em blocos convencionais em circuitos lógicos digitais.

2024, International journal of engineering research and technology

This paper presents optimization of flicker noise of MOS transistor using genetic algorithm(GA), which is the most important evolutionary algorithm. GA is mainly used for optimization of non linear function. It finds the best solution for an objective function. GA starts with the population of a set of chromosomes choosing randomly. One then evaluates this structure and allocates reproductive opportunities in such a way that those chromosomes which have a better solution for the particular problem are given more chances than those chromosomes which have poor chances. In this paper the flicker noise of MOS transistor has been optimized using GA considering variable frequency (f) and channel length (L) of MOS transistor. MATLAB software has been used to run the GA. Optimization results are satisfactory and have been presented in this paper.

2024, International journal of engineering research and technology

2024, Computer Applications in Engineering Education

Some engineering concepts have been proven to be very important not only in engineering degrees but in several areas. This knowledge is difficult to grasp under certain circumstances, and sometimes prior training is needed. This is a special challenge in full or part remote education. Simulations may help in this area, but truly experimental lab practices are crucial to grasp all the required knowledge and not only for fundamental information but for complex or indirect knowledge, where students can apply what they have learnt in classes. In this paper, we have worked on a concept to help professors and students to get new concepts in a more time‐efficient and safe manner, using dynamic reconfiguration in Field‐Programmable Analog Array. This solution can be easily applied to traditional or remote labs in less time than usual practices, so students can learn more in the same amount of time, especially when time is a constraint.

2023, 2011 IEEE International Conference on Pervasive Computing and Communications Workshops (PERCOM Workshops)

Efficient monitoring and control of wastewater treatment plants (WWTPs) has become an important public issue as the cost of electricity continues to grow and the quality requirements of processed water tightens. However, the development, deployment, and maintenance of highly efficient monitors and controllers for wastewater processing tanks are significantly challenging. Self-powered, wireless sensor networks (WSNs) are an ideal candidate for this application, since their deployment would have the least impact on the existing infrastructure. A novel wireless sensor network is presented in this paper that integrates microbial fuel cells (MFCs), fieldprogrammable analog arrays (FPAAs), and low-power networking protocols into the sensors to make them self-powered, highly flexible, and adaptive. MFCs convert chemicals in the waste water into electrical energy, while FPAAs provide a means of performing ultra-low-power, real-time, and adaptive processing of the sensor signals. This design achieves sustainable monitoring and control of wastewater treatment with minimal impact to existing infrastructure.

2023, Journal de physique

The effects of low frequency sound on the changes of morphology of the spectral power density function of EEG signals were studied as a part of the research program f=40 Hz, Lp = 110 dB HP. The research program involved 33 experiments. A quantitative analysis was conducted of the driving response effect for the fundamental frequency and its harmonics to find the frequency of the driving response effect occurrence depending on the sex of participants.

2023, Journal de Physique IV (Proceedings)

2023, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware

2023, Frontiers in Neuroscience

Intelligent sensor systems are essential for building modern Internet of Things applications. Embedding intelligence within or near sensors provides a strong case for analog neural computing. However, rapid prototyping of analog or mixed signal spiking neural computing is a non-trivial and time-consuming task. We introduce mixed-mode neural computing arrays for near-sensor-intelligent computing implemented with Field-Programmable Analog Arrays (FPAA) and Field-Programmable Gate Arrays (FPGA). The combinations of FPAA and FPGA pipelines ensure rapid prototyping and design optimization before finalizing the on-chip implementations. The proposed approach architecture ensures a scalable neural network testing framework along with sensor integration. The experimental set up of the proposed tactile sensing system in demonstrated. The initial simulations are carried out in SPICE, and the real-time implementation is validated on FPAA and FPGA hardware. KEYWORDS computing arrays, field programmable analog arrays, leaky integrate and fire neuron, tactile sensing system, field programmable gate arrays Frontiers in Neuroscience frontiersin.org

2023

Dynamic reconfigurable system came in to limelight in the current generation of VLSI design. Till now area, performance, cost and power are the priorities of design engineers overlooking the Multifunctionality of a single system design. Many researchers are focused on digital VLSI system as compared to the analog VLSI system, it is because of digital system is highly atomized and number of testing hardware and software platforms are available Also very few parameter are sensitive to input as compare to the analog system design. In this paper general concept of dynamic reconfiguration for various analog system design and application is illustrate Keywords-Analog, Digital, Reconfigurable FPGA, FPAA, VLSI. -------------------------------------------------------------------------------------------------------------------------------------Date of Submission: 15-03-2018 Date of acceptance: 30-03-2018 -----------------------------------------------------------------------------------------...

2023

The relatively new field of Evolvable Harding for rapid solution testing (a common bottleneck in many evolutionary algorithms). Some of the pioneering work in this area was done by Higuchi [5] and Thompson The other circuit design domain and the focus of this paper is analog circuitry. Analog circuits are of great importance in electronic system design since the world is fundamentally analog in nature. While the amount of digital design activity far outpaces that of analog design , uu)stdigitalsyst(_rns reqttir(_ ;taah)g m(),ht[es for int('rfa('ing t() the ext(,rmd world. Te('hniques for analog (:ir('iiit iI(_sigii ;uitoination t)egan appi:ariug al)out two (l(',_a(h,._ .'_g() ((:.g., [_01). Etf,,rts .si._ te('hniqu(_ fr,)in evoillti()n;try (:()UlliUti).tion have appeared over the last few y(;ars. Tlii,se inchi(le the I1_ of gem:tic algorithms (GAs) {7i t,) seh;ct filter c()mp()t,,at sizes [_], t() select filter top(Jhigi(;s [3J, and to design operational amplifiers using a sniall set of topologies [12 i. Various analog filter design prol)lems have been solved using genetic programruing (e.g., It li) , and an overview of these techniques, including eight analog circuit synthesis problems, is found in llOl.

2023, Microelectronics and solid state electronics

We propose a comp rehensive design procedure to design Field-programmable/Reconfigurable Analog Integrated CMOS circu its. Instead of repeatedly iterative simu lation steps to achieve desired design specifications by fine tuning the W/L rat ios of the FETs, we use first order classroom equations to achieve central value o f desired specifications and then execute a customized fine tuning of specifications to the customers requirement with the help of Floating-gate Transistors FGMOS. To demonstrate the proposed design cycle, a modified h igh frequency/RF Operational Transresistance Amplifier (OTRA) CM OS circuit is designed where t ransresistance gain and input output low impedances are programmab le, independently to desired values within a specific field range, usin g FGMOSs. In FGM OS the programmab le charge at floating-gate using external voltages can results in threshold voltage field-programming, which in turn program the design (OTRA) specifications. With specific sizing and biasing condition, the transresistance can be programmed fro m 0.5koh m to 6koh m, input and output impedance fro m 600ohm to 10Koh m, while o ffset current can also be compensated independently using respective FGMOSs with 13-bit programming precision. However the final circu it, with four FGM OS occupies 75µm × 64µm ch ip area. The design also consumes less power, total power consumption is about 3.96mW and show good thermal stability as output voltage variation with temperature is about 25µV/°C.

2023, IEEE Transactions on Circuits and Systems I: Regular Papers

This paper reports synthesis methodologies for linear analog circuits. A generalized multi-input operational transconductance amplifier (OTA) network has been synthesized that can be easily programmed to realize different analog functions. The design of the multifunction network has been realized without any switches. The inherent characteristic of OTA as a voltage-to-current (-) converter with differential input has been exploited in the synthesis procedure. Efficient analog circuits synthesized with programmable OTA network are reported along with simulation results. The theoretical analysis supported by extensive experimental results confirms low sensitivity, high-frequency response, and efficient programmability of the proposed OTA network to realize different types of filters. Index Terms-Band-pass filter (BPF), band-reject filter (BRF), high-pass filter (HPF), low-pass filter (LPF), operational transconductance amplifier (OTA), synthesis.

2023, Anais do XXV Simpósio Brasileiro de Telecomunicações

Resumo-O uso de chips de FPGA vem crescendo nasúltimas duas décadas devido a sua capacidade de reconfiguração pelo usuário e os avanços de ferramentas de prototipagem rápida. Sendo assim, este artigo apresenta o projeto de uma função exponencial de alto-desempenho para um chip FPGA (Field Programmable Gate Array) da Xilinx, utilizando a ferramenta de prototipagem rápida Xilinx System Generator for DSP T M e uma placa de desenvolvimento da Nallatech XtremeDSP Kit-IV com uma Virtex-4SX. Este trabalho mostra uma forma eficiente de implementação em hardaware da função exponencial visando o uso em sistemas de comunicações.