Reconfigurable Hardware Research Papers - Academia.edu (original) (raw)

This paper proposes a new algorithm for solving the Boolean satisfiability (SAT) problem. On the basis of this algorithm a software/reconfigurable hardware SAT solver was designed, implemented and compared to a similar realization of the Davis-Putnam-like method. The satisfier suggested uses an application-specific approach, thus an instance- specific hardware compilation is completely avoided.

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- SAT Solver Design, Reconfigurable Hardware, Boolean Satisfiability
- by Javier Resano
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- Geophysics, Image Processing, Remote Sensing, Hyperspectral remote sensing
- by Paul Beckett
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- Computer Architecture, Reconfigurable Hardware, MIMD, Programming Paradigm
- by Daniel Mesquita
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- FPGA, Cryptography, Reconfigurable Hardware, Modular multiplication

A large number of reconfigurable hardware technologies have been proposed both in academia and commercially (some of them in their first market steps). They can be roughly classified in three major categories: a) Field Programmable Gate Arrays (FPGAs), b) integrated circuit devices with embedded reconfigurable resources and c) embedded reconfigurable cores for Systems-on-Chip (SoCs). In this chapter representative commercial technologies are discussed and their main features are presented 1 .

- by Konstantinos Masselos
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- Reconfigurable Hardware, FPGAs
- by Miriam Leeser
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- Reconfigurable Hardware, Software Implementation
- by Lech Jóźwiak and +1
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- Embedded Systems, Computer Aided Design, Computer Hardware, Coding
- by thuy dung Nguyen
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- Privacy, Embedded Systems, Field-Programmable Gate Arrays, Control Systems
- by Georgi Gaydadjiev
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- Field-Programmable Gate Arrays, Hardware, Reconfigurable Hardware, Acceleration
- by Peter Janacik
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- Information Technology, Embedded Systems, Resource Allocation, Internet of Things
- by E. Cabal-yepez
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- Engineering, Technology, Vibrations, Safety

In recent years, Field Programmable Gate Arrays (FP-GAS) have become sufficiently capable to implement com-plex networking applications directly in hardware. By using hardware that can be reprogrammed, network equipment can dynamically... more

- by Marcel Waldvogel and +1
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- Routing, Field-Programmable Gate Arrays, Internet Routing Protocol, Hybrid Intelligent Systems
- by Jörg Lotze and +1
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- Distributed Computing, Cognitive radio, Design method, Reconfigurable Hardware
- by Miguel Figueroa
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- Embedded Systems, Computer Aided Design, Computer Hardware, Coding
- by Kanwaldeep Sobti
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- Distributed Computing, Image Processing, Signal Processing, Computer Hardware
- by Fusun Ozguner
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- Computer Science, Reconfigurable Computing, Scheduling, Parallel Processing

Abstract. Elliptic Curve Public Key Cryptosystems (ECPKC) are be-coming increasingly popular for use in mobile appliances where band-width and chip area are strongly constrained. For the same level of secu-rity, ECPKC use much smaller key... more

- by John W Lockwood
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- Cryptography, Field-Programmable Gate Arrays, Authentication, Energy Management

In this paper, we present the results of the first phase of a project aimed at implementing a full suite of IPSec cryptographic transformations in reconfigurable hardware. Full implementations of the new Advanced Encryption Standard, Rijndael, and the older American federal standard, Triple DES, were developed and experimentally tested using the SLAAC-1V FPGA accelerator board, based on Xilinx Virtex 1000 devices. The experimental clock frequencies were equal to 91 MHz for Triple DES, and 52 MHz for Rijndael. This translates to the throughputs of 116 Mbit/s for Triple DES, and 577, 488, and 423 Mbit/s for Rijndael with 128-, 192-, and 256-bit keys respectively. We also demonstrate a capability to enhance our circuit to handle the encryption and decryption throughputs of over 1 Gbit/s regardless of the chosen algorithm. Our estimates show that this gigabit-rate, double-algorithm, encryption/ decryption circuit will fit in one Virtex 1000 FPGA taking approximately 80% of the area.

- by Peter Bellows
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- Information Security, Reconfigurable Hardware, Experimental Tests
- by Roland Kasper
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- Signal Processing, Mechatronics, FPGA, Adaptive Control
- by Marcel Waldvogel and +1
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- Computer Networks, Computer Hardware, Protocols, Reconfigurable Hardware
- by Pradeep Fernando
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- Genetics, Vlsi Design, Genetic Algorithm, Robust optimization

Due to the emergence of portable devices that must run complex dynamic applications there is a need for flexible platforms for embedded systems. Runtime reconfigurable hardware can provide this flexibility but the reconfiguration latency can significantly decrease the performance. When dealing with task graphs, runtime support that schedules the reconfigurations in advance can drastically reduce this overhead. However, executing complex scheduling heuristics at runtime may generate an excessive penalty. Hence, we have developed a hybrid design-time/runtime reconfiguration scheduling heuristic that generates its final schedule at runtime but carries out most computations at design-time. We have tested our approach in a PowerPC 405 processor embedded on a FPGA demonstrating that it generates a very small runtime penalty while providing almost as good schedules as a full runtime approach.

- by carlos gonzalez
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- Computer Hardware, Computer Software, Reconfigurable Hardware, FPGAs
- by Kamran Eshraghian
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- Signal Processing, Networking, Speculation, Reconfigurable Hardware

Implementation of RNS addition and RNS multiplication into FPGAs (Extended Abstract) Luiz Maltar CB, Felipe MG França, Vladmir C. Alves and Cláudio L. Amorim COPPE - Universidade Federal do Rio de Janeiro Caixa Postal 68511, Postal Code... more

- by Ahmad Razlan Yusoff
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- Engineering, Genetic Algorithms, Embedded Systems, Genetic Algorithm

This chapter introduces the reader to main concepts of reconfigurable
computing and reconfigurable hardware. Different types of reconfiguration are
discussed. A detailed classification of reconfigurable architectures with respect
to the granularity of their building blocks, the reconfiguration scheme and the
system level coupling is also presented.

- by Jorge Cerqueira
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- Hardware Design, Case Study, Reconfigurable Hardware, Software Implementation

Evolvable hardware (EHW) is a set of techniques that are based on the idea of combining reconfiguration hardware systems with evolutionary algorithms. In other word, EHW has two sections; the reconfigurable hardware and evolutionary algorithm where the configurations are under the control of an evolutionary algorithm. This paper, suggests a method to design and optimize the synchronous sequential circuits. Genetic algorithm (GA) was applied as evolutionary algorithm. In this approach, for building input combinational logic circuit of each DFF, and also output combinational logic circuit, the cell arrays have been used. The obtained results show that our method can reduce the average number of generations by limitation the search space.

This paper presents a reconfigurable hardware architecture for Public-key cryptosystems. By changing the connections of coarse grain Carry-Save Adders (CSAs), the datapath provides a high perfor- mance for both RSA and Elliptic Curve Cryptography (ECC). In addi- tion, we introduce another reconfigurability for the flip-flops in order to make the best of hardware resources. The results of FPGA implemen- tation

- by Nele Mentens
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- Electronics, Cryptography, FPGA implementation, Reconfigurable Hardware