Direct Memory Access (DMA) Controller (original) (raw)

Last Updated : 11 Apr, 2026

In modern computer systems, transferring data between input/output (I/O) devices and memory can slow performance if the CPU manages every step. To overcome this, a Direct Memory Access (DMA) Controller is used. It enables I/O devices to transfer data directly to or from memory without heavy CPU involvement, improving speed and efficiency.

• It generates memory addresses and controls timing for efficient data movement.
• Once initialize by the CPU, it operates independently to complete the transfer.

Block Diagram of DMA Controller

Types

• **Burst Mode (Block Transfer): DMA transfers entire data block at once and CPU is halted temporarily.
• **Cycle Stealing Mode: DMA transfers one word at a time, allowing CPU to execute between transfers.
• **Transparent Mode: DMA transfers data only when CPU is idle, so CPU operation is not affected.

Working of DMA Controller

The DMA controller registers have three registers as follows.

• **Address register: It contains the address to specify the desired location in memory.
• **Word count register: It contains the number of words to be transferred.
• **Control register: It specifies the transfer mode.

All registers in the DMA appear to the CPU as I/O interface registers. Therefore, the CPU can both read and write into the DMA registers under program control via the data bus.

The figure below shows the block diagram of the DMA controller. The unit communicates with the CPU through the data bus and control lines. The CPU selects DMA registers using address lines and control signals.

RD (Read) and WR (Write) are control signals used to specify read or write operations. When BG (bus grant) input is 0, the CPU can communicate with DMA registers. When BG (bus grant) input is 1, the CPU has relinquished the buses and DMA can communicate directly with the memory.

Working Diagram of DMA Controller

The CPU initializes the DMA by sending the given information through the data bus.

• The starting address of the memory block where the data is available (to read) or where data are to be stored (to write).
• It also sends word count which is the number of words in the memory block to be read or written.
• Control to define the mode of transfer such as read or write.
• A control to begin the DMA transfer

Modes of Data Transfer in DMA

There are 3 modes of data transfer in DMA that are described below.

**Burst Mode

• In Burst Mode, the DMA controller takes full control of the system bus and transfers the entire block of data in one go.
• The bus is not handed back to the CPU until the entire data transfer is complete.
• This mode is efficient for large data transfers but can delay CPU operations.

**Transparent Mode

• In Transparent Mode, the DMA controller transfers data only when the CPU is not using the system bus.
• It effectively sneaks in transfers during idle CPU cycles, ensuring the CPU is never interrupted.
• Best when CPU performance is critical and some delay in data transfer is acceptable.

**Cycle Stealing Mode

• In Cycle Stealing Mode, the DMA controller transfers one byte (or word) at a time and then releases control of the bus back to the CPU.
• This mode generates frequent bus requests but allows the CPU to execute instructions in between DMA transfers.
• Useful when the DMA task is important but should not entirely block the CPU, such as in audio or video streaming.