DMA Controller 8257/8237 (original) (raw)

Last Updated : 21 Apr, 2026

Direct Memory Access (DMA) is a technique that allows peripheral devices to transfer data directly to or from memory with minimal CPU intervention, significantly improving data transfer speed and efficiency. The Intel 8257 and 8237 are programmable DMA controllers widely used in microprocessor systems for high-speed data transfers

DMA Controller Architecture (8257/8237)

This problem of slow data transfer between the input-output port and memory or between two memories is reduced by implementing the Direct Memory Access (DMA) technique. This is faster, as the microprocessor/computer is bypassed, and the control of address, data, and control bus is temporarily given to DMA controller.

• HOLD - Hold Signal
• HLDA - Hold Acknowledgement
• DREQ - DMA Request
• DACK - DMA acknowledgement

Suppose a floppy drive that is connected at input-output port wants to transfer data to memory, the following steps are performed:

• **DMA Request Initiation: The floppy drive asserts a **DREQ signal to the DMA controller, requesting DMA service.
• **Bus Control Request: The DMAC sends a **HOLD signal to the CPU to gain control of the address and data buses.
• **CPU Relinquishes Control: Upon accepting the hold request, the CPU completes its current bus activities, then sends an **HLDA signal back to the DMAC, acknowledging the transfer of bus authority.
• **DMA Acknowledgement: The DMAC issues a **DACK signal to the floppy drive, confirming that DMA service will begin.
• **Data Transfer Execution: DMAC manages data movement from the floppy drive to memory using I/O read and memory write signals, all without CPU intervention.
• **DMA Completion: After the required number of memory locations are filled, DMAC returns control of the buses to the CPU, resuming normal processor operation.

Features of 8257/8237

• Four independent DMA channels, each programmable for read, write, or verify operations.​
• Each channel can transfer up to 64 KB of data.​
• Supports both single and cascade modes for flexible system expansion.​
• Generates MARK signal after every 128 bytes transferred, useful for block transfers.​
• Operates in master and slave modes for different system configurations.

**Modes of DMAC:

**1. Single Mode - Only one DMA controller (DMAC) is connected to the system bus. It manages data transfer for a single channel at a time between memory and I/O devices.

DMA Single Mode Operation

**2. Cascade Mode - Multiple DMA controllers are connected together (cascaded) to support more channels. One controller acts as the master, while the others act as slaves, allowing expansion of the number of devices that can perform DMA operations.

DMA Cascade Mode Architecture