Asynchronous Down Counter (original) (raw)
Last Updated : 23 Jul, 2025
Counters are sequential circuits used to count the clock pulses that occur at regular intervals. They are used to measure the time and frequency. They are of two types:
- Asynchronous counter
- Synchronous counter
In the asynchronous counter, an external clock pulse is provided for only the first flip flop, thereafter the output of the 1st FF acts as a clock pulse for the second FF and so on. In the case of synchronous FFs, all the flip flops are triggered simultaneously by an external clock pulse.
Asynchronous Counter
An asynchronous counter is also known as a ripple counter. It is a sequential circuit in which the flip-flops are not triggered simultaneously. Only the first flip-flop receives the external clock pulse directly and the output of each flip-flop serves as the clock input for the next one in the chain. As a result, the clock signals "ripple" through the flip-flops, causing a slight delay in the overall response. It can be categorized into two:
- **Asynchronous Up Counter: A counter that increases its binary value with each clock pulse.
- **Asynchronous Down Counter: A counter that decreases its binary value with each clock pulse
Read more about designing of asynchronous counter.
**3 Bit Asynchronous Down Counter
- For the 3 bit counter, we require 3 flip flops and we can generate 23 = 8 state and count(111 110 ... 000).
- We can generate down counting states in an asynchronous down counter by two ways.
**Method 1
In this implementation, the clock pulse(of 50% duty cycle) is given to only the first FF. Thereafter, the output of the first FF is feed as a clock to second FF and the output of the second FF is feed as the clock for the third FF. But the complemented output is taken from each FF(i.e. same as Up counter but output states are complemented). Here QA is LSB and QC is MSB.
**State table
**Circuit Implementation of Method 1
- The -ve edge clock pulse is provided to 1st counter. Therefore, the output state of the first counter(i.e. QA) will be toggled at every falling edge of the clock pulse.
- As the QA is feed as a clock to the second FF, therefore the output state (i.e. QB) will be toggled at every falling edge of QA.
- In the same manner, the QB acts as clock for the third FF, therefore the output state (QC) of the third FF will be toggled for every falling edge of QB.
- As we know, this is the working of UP counter, but here the output is taken as in complemented form (i.e. Q'C Q'B Q'A), therefore we get the complemented outputs(i.e. down counting 111 to 000)
- After the 8th falling edge of the external clock pulse, the counter is reset to 000.
Timing diagram for circuit
**Method 2
In this implementation, the clock pulse is given to only the first FF. Thereafter, the complemented output of the first FF(Q'A) is feed as a clock to the second FF and complemented output(i.e. Q'B) of the second FF is feed as a clock for the third FF. But the output(Q) is taken from each FF.
By both implementations, we can acquire the same counting states.
**Explanation
- Here the -ve edge clock pulse is used(i.e. the counter state transition can occur only at falling edge of the clock pulse) , therefore toggling will take place.
- All the counter states are generated by the frequency division.
- Initially QA =0 QB =0 and QC= 0.
**Circuit Implementation of Method 2
- The -ve edge clock pulse is provided to 1st counter. Therefore, the output state of the first counter(i.e. QA) will be toggled at every falling edge of the clock pulse.
- As the complemented output(Q'A) is feed as a clock to second FF, therefore the output state (i.e. QB) will be toggled at every falling edge of Q'A.
- In the same manner, the Q'B acts as a clock for the third FF, therefore the output state (QC) of the third FF will be toggled for every falling edge of Q'B.
- In this case, the outputs from the three FF are taken as (QC QB QA).
- After the 8th falling edge of the external clock pulse, the counter is reset to 000.
- Here, the down counting states can be acquired after first -ve edge clock pulse(i.e. after first -ve pulse the counting output becomes 111).
Timing diagram for circuit
**Advantages of Asynchronous Counter
- Due to accumulation of propagation delay, they are used in low speed circuits.
- They are simple to design.
- They are used in mod n counter, and in divide by n counter that divides the input by n(i.e. n is integer).
**Disadvantages of Asynchronous Counter
- As the number of flip-flops increases, the propagation delay also increases.
- For high clock frequencies, counting errors may occur because of propagation delay.
**For example:-Due to propagation delay(by counter), the toggling action takes place after some delay, so by this wrong counting states may be generated. - In the case of truncated counter (i.e. in mod counters), extra feedback logic(i.e. logic gate) is required.