Combinational circuits using Decoder (original) (raw)

Last Updated : 26 Nov, 2025

Combinational circuits utilizing decoders are basic parts in a computerized plan, assuming a significant part in making an interpretation of parallel data into noteworthy results. Decoders are combinational rationale gadgets that convert twofold information signals into an extraordinary arrangement of results, each addressing a particular blend of information values. They are instrumental in different applications, for example, memory address unraveling, information directing, and show frameworks. By utilizing decoders, planners can make productive and flexible circuits that work with complex rationale activities and improve framework usefulness. Understanding the coordination of decoders into combinational circuits is fundamental for streamlining computerized frameworks and accomplishing dependable execution.

What is Combinational Circuit?

A combinational circuit is a kind of computerized circuit where the result is exclusively reliant upon the ongoing contributions, with no memory or input components included. This implies that the result is an immediate consequence of the info values out of the blue, reflecting quick changes immediately. Combinational circuits perform different legitimate tasks like expansion, deduction, and information-directing through parts like rationale doors, multiplexers, and decoders. They are major in advanced frameworks for making useful units like number-crunching rationale units (ALUs) and information selectors, offering unsurprising and direct conduct in view of their feedback conditions.

What is Decoder?

A Decoder is a computerized circuit that changes over twofold data from a n-bit contribution to a one-of-2^n result, where just a single result line is enacted at a time. It basically makes an interpretation of double code into a particular arrangement of results, empowering the determination of a solitary result line in view of the twofold information value. Decoders are broadly utilized in different applications, for example, memory address deciphering, information directing, and show frameworks (e.g., seven-portion shows). For instance, a 3-to-8 decoder has 3 info lines and 8 result lines, where every mix of the 3 info bits compares to one dynamic result line.

**Decoder as a De-Multiplexer

A Decoder with Enable input can function as a demultiplexer. A demultiplexer is a circuit that receives information from a single line and directs it to one of

2^n

possible output lines.

A

2^n

demultiplexer receives as input,

n

selection lines and one Input line. These selection lines are used to select one output line out of

2^n

possible lines. To implement a

2^n

demultiplexer, we use a

n:2^n

decoder with Enable input. The

n

selection lines of the demultiplexer are the

n

input lines that the decoder gets and the one input line of demultiplexer is the Enable input of the Decoder.

Making 1:4 demultiplexer using 2:4 Decoder with Enable input. Let A, B be the selection lines and EN be the input line for the demultiplexer.
The decoder shown below functions as a 2:4 demultiplexer when EN is taken as a data input line and A and B are taken as the selection inputs. The single input variable E has a path to all four outputs, but the input information is directed to only one of the output lines, as specified by the binary combination of the two selection lines A and B. This can be verified from the truth table of the circuit.

333

**Truth Table-

\begin{tabular}{|c|c|c||c|c|c|c|} \hline E & A & B & D_0 & D_1 & D_2 & D_3\\ \hline \hline 0 & X & X & 0 & 0 & 0 & 0\\ \hline 1 & 0 & 0 & 1 & 0 & 0 & 0\\ \hline 1 & 0 & 1 & 0 & 1 & 0 & 0\\ \hline 1 & 1 & 0 & 0 & 0 & 1 & 0\\ \hline 1 & 1 & 1 & 0 & 0 & 0 & 1\\ \hline \end{tabular}

**Combinational Logic Implementation using Decoder

A decoder takes

n

input lines and has

2^n

output lines. These output lines can provide the

2^n

minterms of

n

input variables.
Since any Boolean function can be expressed as a sum of minterms, a decoder that can generate these minterms along with external OR gates that form their logical sums, can be used to form a circuit of any boolean function.

For example, if we need to implement the logic of a full adder, we need a 3:8 decoder and OR gates. The input to the full adder, first and second bits and carry bit, are used as input to the decoder. Let x, y and z represent these three bits. Sum and Carry outputs of a full adder have the following truth tables-

\begin{tabular}{|c|c|c||c|c|} \hline x & y & z & S & C\\ \hline \hline 0 & 0 & 0 & 0 & 0\\ \hline 0 & 0 & 1 & 1 & 0\\ \hline 0 & 1 & 0 & 1 & 0\\ \hline 0 & 1 & 1 & 0 & 1\\ \hline 1 & 0 & 0 & 1 & 0\\ \hline 1 & 0 & 1 & 0 & 1\\ \hline 1 & 1 & 0 & 0 & 1\\ \hline 1 & 1 & 1 & 1 & 1\\ \hline \end{tabular}

Therefore we have-

S = \sum (1, 2, 4, 7)
C = \sum (3, 5, 6, 7)

The following circuit diagram shows the implementation of Full adder using a 3:8 Decoder and OR gates.

**Advantages of Combinational circuits using Decoder

**Disadvantages of Combinational circuits using Decoder

Application of Combinational circuits using Decoder