Paged Segmentation and Segmented Paging (original) (raw)

Last Updated : 5 Jan, 2026

Paged segmentation and segmented paging are two memory management techniques that combine the principles of segmentation and paging to overcome their individual drawbacks. While they both use a two-level address translation system, the key difference lies in the organization of the tables and how they handle fragmentation.

Major Limitation of Single Level Paging

In single-level paging, the page table can become very large if the logical address space is big.

• Example: With a 32-bit address and 4 KB page size, there are 2202^{20}220 pages , page table size ≈ 4 MB per process.
• Since each process has its own page table, huge memory is wasted.
• For a 64-bit address space, a single page table may not even fit in main memory.
• Many entries are often unused/invalid, as processes don’t use the entire logical address space.

Page table with invalid entries

To overcome this flaw, we use Segmented Paging.

Segmented Paging

Segmented Paging is a hybrid memory allocation technique that uses the benefits of both segmentation and paging.

To understand segmented paging in detail, refer article: Segmented Paging

Paged Segmentation

In segmented paging, each process has a different number of segments, and the segment tables can grow very large. This variation may lead to external fragmentation because of uneven segment table sizes. To solve this, paged segmentation is used, where the segment table itself is divided into pages.

The logical address generated by the CPU is now divided into four parts:

• Page number 1 (to locate the page of the segment table),
• Segment number (to identify the segment),
• Page number 2 (to find the page within that segment),
• Offset (to locate the exact word/byte inside the page).

This approach allows the system to manage even large segment tables efficiently, ensuring better use of memory while still preserving the logical view of segmentation.

Paged Segmentation

Address translation in paged segmentation:

**1. Logical Address Breakdown: The CPU generates a logical address divided into four fields: s1 | s2 | p | w.

• s1: Index into the segment directory (page table of the segment table).
• s2: Index into the pages of the segment table.
• p: Index into the page table of that segment.
• w: The word/offset inside the physical page.

**2. Segment Directory (s1)

• The first part (s1) selects an entry in the segment directory.
• This points to a page containing part of the segment table.

**3. Pages of Segment Table (s2)

• The second part (s2) selects the required page of the segment table.
• This entry gives the base address of the page table for that segment.

**4. Page Tables (p)

• The third part (p) selects an entry in the page table of the segment.
• This entry points to the actual frame in physical memory.

**5. Word/Offset (w): Finally, the offset (w) is added to reach the exact word/byte in physical memory.

**Advantages of Paged Segmentation

• **Efficient memory use: Paging of segment tables removes external fragmentation.
• **Supports large address spaces: Segment tables can be very large but are handled flexibly by paging.
• **Protection and modularity: Segments (code, data, stack) remain logically separated.

**Disadvantages of Paged Segmentation

• **Complexity: Multiple tables (segment directory + page tables) increase management overhead.
• **Higher latency: More levels of translation slow down memory access.
• **Storage overhead: Extra tables require additional memory space.