GATE CS 2022 (original) (raw)

Consider the following threads, T1, T2, and T3 executing on a single processor, synchronized using three binary semaphore variables, S1, S2, and S3, operated upon using standard wait() and signal(). The threads can be context switched in any order and at any time.

Which initialization of the semaphores would print the sequence BCABCABCA….?

Which one of the following statements is TRUE for all positive functions _f (_n)?

• [Tex]f(n^{2}) = \theta (f(n^{2})) [/Tex], when _f (_n) is a polynomial
• [Tex]f(n^{2}) = o (f(n^{2}))[/Tex]
• [Tex]f(n^{2}) = O(f(n^{2})) [/Tex], when f (n) is an exponential function
• [Tex]f(n^{2}) = Ω(f(n^{2}))[/Tex]

What is printed by the following ANSI C program?

#include<stdio.h>
int main(int argc, char *argv[])
{
int x = 1, z[2] = {10, 11};
int *p = NULL;
p = &x;
*p = 10;
p = &z[1];
*(&z[0] + 1) += 3;
printf("%d, %d, %d\n", x, z[0], z[1]);
return 0;
}

In a relational data model, which one of the following statements is TRUE?

• A relation with only two attributes is always in BCNF.
• If all attributes of a relation are prime attributes, then the relation is in BCNF.
• Every relation has at least one non-prime attribute
• BCNF decompositions preserve functional dependencies

Let R1 and R2 be two 4-bit registers that store numbers in 2’s complement form. For the operation R1+R2, which one of the following values of R1 and R2 gives an arithmetic overflow?

Which one of the following regular expressions correctly represents the language of the finite automaton given below

• (ba*a+ ab*b)* (ab* + ba*)

Which of the following statements is/are TRUE?

• Every subset of a recursively enumerable language is recursive.
• If a language L and its complement L are both recursively enumerable, then L must be recursive.
• The complement of a context-free language must be recursive
• If L1 and L2 are regular, then L1∩ L2 must be deterministic context-free

Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a write through cache. Which of the following statements is/are FALSE?

• Each cache block in WB and WT has a dirty bit
• Every write hit in WB leads to a data transfer from cache to main memory.
• Eviction of a block from WT will not lead to data transfer from cache to main memory
• A read miss in WB will never lead to eviction of a dirty block from WB

Which one of the following facilitates the transfer of bulk data from hard disk to main memory with the highest throughput?

• Interrupt driven I/O transfer
• Polling based I/O transfer

A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X2 operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for X1 and X2. If the BPU has a prediction accuracy of 80%, the speed up (rounded off to two decimal places) obtained by X2 over X1 in executing P is____________.

There are 65 questions to complete.

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