CD40110B data sheet, product information and support (original) (raw)

CMOS Decade Up-Down Counter/Latch/Display Driver

Function Counter Bits (#) 7 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Catalog

PDIP (N) 16 181.42 mm² 19.3 x 9.4

Separate clock-up and clock-down lines
Capable of driving common cathode LEDs and other displays directly
Allows cascading without any external circuitry
100% tested for quiescent current at 20 V
Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (full package-temperature range) =
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V
5 V, 10 V and 15 V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices".
Applications
- Rate comparators
- General counting applications where display is desired
- Up-down counting applications where input pulses are random in nature
Separate clock-up and clock-down lines
Capable of driving common cathode LEDs and other displays directly
Allows cascading without any external circuitry
100% tested for quiescent current at 20 V
Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (full package-temperature range) =
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V
5 V, 10 V and 15 V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices".
Applications
- Rate comparators
- General counting applications where display is desired
- Up-down counting applications where input pulses are random in nature

CD40110B is a dual-clocked up/down counter with a special preconditioning circuit that allows the counter to be clocked, via positive going inputs, up or down regardless of the state or timing (within 100 ns typ.) of the other clock line.

The clock signal is fed into the control logic and Johnson counter after it is preconditioned. The outputs of the Johnson counter (which include anti-lock gating to avoid being locked at an illegal state) are fed into a latch. This data can be fed directly to the decoder through the latch or can be strobed to hold a particular count while the Johnson counter continues to be clocked. The decoder feeds a seven-segment bipolar output driver which can source up to 25 mA to drive LEDs and other displays such as low-voltage fluorescent and incandescent lamps.

A short durating negative-going pulse appears on the BORROW output when the count changes from 0 to 9 or the CARRY output when the count changes from 9 to 0. At the other times the BORROW and CARRY outputs are a logic 1.

The CARRY and BORROW outputs can be tied directly to the clock-up and clock-down lines respectively of another CD40110B for easy cascading of several counters.

The CD40110B types are supplied in 16-0lead dual-in-line ceramic packages (D and F suffixes), and 16-lead dual-in-line plastic package (E suffix), and also available in chip form, (H suffix).

The CARRY and BORROW outputs can be tied directly to the clock-up and clock-down lines respectively of another CD40110B for easy cascading of several counters.

The CD40110B types are supplied in 16-0lead dual-in-line ceramic packages (D and F suffixes), and 16-lead dual-in-line plastic package (E suffix), and also available in chip form, (H suffix).

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CD40110B data sheet, product information and support (original) (raw)

CMOS Decade Up-Down Counter/Latch/Display Driver

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