Mohammad Arif Sobhan Bhuiyan | Xiamen University Malaysia (original) (raw)

Papers by Mohammad Arif Sobhan Bhuiyan

IET Circuits, Devices & Systems, 2020

The preamplifier module is a crucial element while designing dynamic latch comparators. The tradi... more The preamplifier module is a crucial element while designing dynamic latch comparators. The traditional double tail comparator utilizes a differential pair as the preamplifier stage. The circuit is generally suffered from high power dissipation and low comparison speed. This research reports the design and implementation of a low-offset, low-power and high-speed dynamic latch comparator. In this work, an enhanced differential pair amplifier is employed in the preamplifier stage, to improve the power dissipation and the comparison speed of the device. A custom latch structure with rigorous transistor sizing was implemented to avoid short circuit current and mismatch in the module. The effective trans-conductance of the cross-coupled transistors of the latch was therefore improved for an optimal time delay solution. The equation associated with the delay was derived and the parameters that embody the speed were identified. The design has been validated by corner analysis and post-layout simulation results in 65 nm CMOS technology process, which reveals that the proposed circuit can operate at a higher clock frequency of 20 GHz with a low-offset of 4.45 mV and 14.28 ps propagation delay, while dissipating only 67.8 μW power consumption from 1 V supply and exhibited lowest PDP of 0.968 fJ. Moreover, the core circuit layout occupies only 183.3 μm 2 .

Electronics, 2019

Power amplifiers (PAs) are among the most crucial functional blocks in the radio frequency (RF) f... more Power amplifiers (PAs) are among the most crucial functional blocks in the radio frequency (RF) frontend for reliable wireless communication. PAs amplify and boost the input signal to the required output power. The signal is amplified to make it sufficiently high for the transmitter to propagate the required distance to the receiver. Attempted advancements of PA have focused on attaining high-performance RF signals for transmitters. Such PAs are expected to require low power consumption while producing a relatively high output power with a high efficiency. However, current PA designs in nanometer and micrometer complementary metal-oxide semiconductor (CMOS) technology present inevitable drawbacks, such as oxide breakdown and hot electron effect. A well-defined architecture, including a linear and simple functional block synthesis, is critical in designing CMOS PA for various applications. This article describes the different state-of-the art design architectures of CMOS PA, including their circuit operations, and analyzes the performance of PAs for 2.4 GHz ISM (industrial, scientific, and medical) band applications.

Sensors, 2021

The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consu... more The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle a large number of pileup events in the High-Luminosity Large Hadron Collider (LHC). A low-noise, wide bandwidth, and ultra-low power FEE for the pixel-strip sensor of the CMS has been designed and simulated in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The design comprises a Charge Sensitive Amplifier (CSA) and a fast Capacitor-Resistor-Resistor-Capacitor (CR-RC) pulse shaper (PS). A compact structure of the CSA circuit has been analyzed and designed for high throughput purposes. Analytical calculations were performed to achieve at least 998 MHz gain bandwidth, and then overcome pileup issue in the High-Luminosity LHC. The spice simulations prove that the circuit can achieve 88 dB dc-gain while exhibiting up to 1 GHz gain-bandwidth product (GBP). The stability of the design was guaranteed with an 82-degree phase margin while 214 ns optimal shaping time was extracted for low-power purposes. The robustness of the design against radiations was performed and the amplitude resolution of the proposed front-end was controlled at 1.87% FWHM (full width half maximum). The circuit has been designed to handle up to 280 fC input charge pulses with 2 pF maximum sensor capacitance. In good agreement with the analytical calculations, simulations outcomes were validated by post-layout simulations results, which provided a baseline gain of 546.56 mV/MeV and 920.66 mV/MeV, respectively, for the CSA and the shaping module while the ENC (Equivalent Noise Charge) of the device was controlled at 37.6 e − at 0 pF with a noise slope of 16.32 e − /pF. Moreover, the proposed circuit dissipates very low power which is only 8.72 µW from a 3.3 V supply and the compact layout occupied just 0.0205 mm 2 die area.

Diagnostics, 2021

A force-invariant feature extraction method derives identical information for all force levels. H... more A force-invariant feature extraction method derives identical information for all force levels. However, the physiology of muscles makes it hard to extract this unique information. In this context, we propose an improved force-invariant feature extraction method based on nonlinear transformation of the power spectral moments, changes in amplitude, and the signal amplitude along with spatial correlation coefficients between channels. Nonlinear transformation balances the forces and increases the margin among the gestures. Additionally, the correlation coefficient between channels evaluates the amount of spatial correlation; however, it does not evaluate the strength of the electromyogram signal. To evaluate the robustness of the proposed method, we use the electromyogram dataset containing nine transradial amputees. In this study, the performance is evaluated using three classifiers with six existing feature extraction methods. The proposed feature extraction method yields a higher pattern recognition performance, and significant improvements in accuracy, sensitivity, specificity, precision, and F1 score are found. In addition, the proposed method requires comparatively less computational time and memory, which makes it more robust than other well-known feature extraction methods.

Diagnistics, 2021

Background: Diabetic peripheral neuropathy (DSPN), a major form of diabetic neuropathy, is a comp... more Background: Diabetic peripheral neuropathy (DSPN), a major form of diabetic neuropathy, is a complication that arises in long-term diabetic patients. Even though the application of machine learning (ML) in disease diagnosis is a very common and well-established field of research, its application in diabetic peripheral neuropathy (DSPN) diagnosis using composite scoring techniques like Michigan Neuropathy Screening Instrumentation (MNSI), is very limited in the existing literature. Method: In this study, the MNSI data were collected from the Epidemiology of Diabetes Interventions and Complications (EDIC) clinical trials. Two different datasets with different MNSI variable combinations based on the results from the eXtreme Gradient Boosting feature ranking technique were used to analyze the performance of eight different conventional ML algorithms. Results: The random forest (RF) classifier outperformed other ML models for both datasets. However, all ML models showed almost perfect reliability based on Kappa statistics and a high correlation between the predicted output and actual class of the EDIC patients when all six MNSI variables were considered as inputs. Conclusions: This study suggests that the RF algorithm-based classifier using all MNSI variables can help to predict the DSPN severity which will help to enhance the medical facilities for diabetic patients.

IEEE Access, 2021

Variation in the electromyogram pattern recognition (EMG-PR) performance with the muscle contract... more Variation in the electromyogram pattern recognition (EMG-PR) performance with the muscle
contraction force is a key limitation of the available prosthetic hand. To alleviate this problem, we propose a
scheme to realize electromyogram signal normalization across channels before feature extraction. The
proposed signal normalization scheme is validated over a dataset of nine transradial amputees that includes
three force levels with six hand gestures. Moreover, we employ three classifiers, namely, linear discriminant
analysis (LDA), support vector machine (SVM) and k-nearest neighbour (KNN), to evaluate the EMG-PR
performance. In addition to the signal normalization scheme, we perform nonlinear transformation of the
features by using the logarithm function. Both schemes facilitate merging of the muscle activation patterns
of different force levels. The experimental results indicate that the force invariant EMG-PR performance (F1
score of at least 3.24% to 4.34%) of the proposed schemes is significantly enhanced compared to that obtained
in recent studies. Therefore, we recommend using these features along with the proposed signal normalization
scheme and nonlinear transformation of the features to improve the force invariant EMG-PR performance.
The proposed feature extraction method achieves the highest F1 score of 91.28%, 91.39% and 90.56% when
using the LDA, SVM and KNN classifiers, respectively.

Micro and Nanosystems, 2018

Background: All modern transceiver circuits utilize high-performance band pass filters for proper... more Background: All modern transceiver circuits utilize high-performance band pass filters for
proper frequency selection led the researchers to inaugurate the journey of CMOS active inductor. The
prime performance requirements of such circuits are very low power dissipation, relatively higher Qfactor with fixed center frequency tuning but a tradeoff among these parameters is inevitable.
Method: A number of active inductor-based band pass filters have been designed over the years to obtain better performance trade-offs and a discussion on these designs is presented from their advantages,
disadvantages and application point of view. The active inductors are capable of working effectively in
band pass filters at very high frequencies up to 11.47 GHz and can be designed to achieve smallest chip
area as low as 0.005 mm2. Besides some essential critical parameters such as high-quality factor, narrow
bandwidth, central frequency tuning, low voltage operation, very small power consumption etc. are also
achievable. Moreover, compared to Gm-C and Q-enhanced LC tank band pass filters, filters with active
inductor show better performance in terms of low power consumption, small silicon area, high Q factor
and tunability.
Conclusion: This review will help the engineers in designing compact and high-performance CMOS
band-pass filter circuits for various RF devices.

Original scientific paper Radio Frequency Identification (RFID) based systems are ubiquitous nowa... more Original scientific paper Radio Frequency Identification (RFID) based systems are ubiquitous nowadays. Band pass filters always play an important role in overall performance of an RFID transponder. In this paper, a band pass filter with a transistor only active inductor is presented for compact high performance reader-less RFID transponder. Post layout simulation result reveals that the centre frequency of the filter can be set to 2,42 GHz frequency with a bandwidth of 38 MHz. The filter core occupies an area of 0,004 mm 2 and dissipates only 1,3 mW at 1,5 V supply voltage. CEDEC 0,18 µm CMOS technology in Mentor Graphics environment has been used for the design of the proposed filter. Dizajn pojasnog filtra u 0,18 μm CMOS za 2,4 GHz RFID transponder bez čitača Izvorni znanstveni članak Sustavi temeljeni na Radio Frequency Identification (RFID) sada su široko rasprostranjeni. Pojasno fazni filtri igraju važnu ulogu u funkcioniranju RFID transpondera. U ovom radu, pojasno fazni filtar s induktorom aktivnim samo s tranzistorom prikazan je za kompaktni RFID transponder bez čitača visokih performansi. Rezultat simulacije rasporeda otkriva da središnja frekvencija filtra može biti postavljena na frekvenciju od 2,42 GHz sa širinom pojasa od 38 MHz. Jezgra filtra zauzima površinu od 0,004 mm 2 i gubi samo 1,3 mW kod napona napajanja od 1,5 V. Predloženi filtar dizajniran je pomoću CEDEC 0,18 μm CMOS tehnologije u Mentor Graphics okruženju. Ključne riječi: aktivni induktor; pojasno fazni filtar; CMOS (dopunski metalno oksidni poluvodič); RFID (radio frekvencijska identifikacija)

The shift register is a type of sequential logic circuit which is mostly used for storing digital... more The shift register is a type of sequential logic circuit which is mostly used for storing digital data or the transferring of data in the form of binary numbers in radio frequency identification (RFID) applications to improve the security of the system. A power-efficient shift register utilizing a new flip-flop with an implicit pulse-triggered structure is presented in this article. The proposed flip-flop has features of high performance and low power. It is composed of a sampling circuit implemented by five transistors, a C-element for rise and fall paths, and a keeper stage. The speed is enhanced by executing four clocked transistors together with a transition condition technique. The simulation result confirms that the proposed topology consumes the lowest amounts of power of 30.1997 and 22.7071 nW for parallel in -parallel out (PIPO) and serial in -serial out (SISO) shift register respectively covering 22 µm 2 chip area. The overall design consist of only 16 transistors and is simulated in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology with a 1.2 V power supply.

The shift register is a type of sequential logic circuit which is mostly used for storing digital... more The shift register is a type of sequential logic circuit which is mostly used for storing digital data or the transferring of data in the form of binary numbers in radio frequency identification (RFID) applications to improve the security of the system. A power-efficient shift register utilizing a new flip-flop with an implicit pulse-triggered structure is presented in this article. The proposed flip-flop has features of high performance and low power. It is composed of a sampling circuit implemented by five transistors, a C-element for rise and fall paths, and a keeper stage. The speed is enhanced by executing four clocked transistors together with a transition condition technique. The simulation result confirms that the proposed topology consumes the lowest amounts of power of 30.1997 and 22.7071 nW for parallel in –parallel out (PIPO) and serial in –serial out (SISO) shift register respectively covering 22 µm 2 chip area. The overall design consist of only 16 transistors and is simulated in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology with a 1.2 V power supply.

A band pass filter is an inherent part of every radio frequency (RF) transceiver. The usage of sp... more A band pass filter is an inherent part of every radio frequency (RF) transceiver. The usage of spiral inductors in band-pass filters cannot overcome limitations such as loss due to parasitic effects, large chip area, low quality factor, less tenability, etc. Therefore, this paper presents an active inductor based design of a second order band-pass filter in 0.18µm complementary metal oxide semiconductor (CMOS) technology for 2.4 GHz radio frequency (RF) applications. The centre frequency of the proposed band pass filter can be adjusted from 1.86 GHz to 3.33 GHz with high Q factor of 250 at 2.45GHz. This filter dissipates only 3.407 mW at 1.5V supply voltage and occupies only 0.0014 mm2 chip area.

In this paper, an active inductor based CMOS low noise amplifier (LNA) has been illustrated for 2... more In this paper, an active inductor based CMOS low noise amplifier (LNA) has been illustrated for 2.4 GHz ISM band RF receivers. The proposed LNA has three stages: the common gate amplifier, the active inductor and the output buffer. The LNA is designed in Silterra 130-nm CMOS process. It operates at 1.2V supply voltage and exhibit a high gain (S21) of 33dB and reverse isolation (S12) of-33.1dB. The power dissipation of the LNA is only 1.51mW with 8.51 dB noise figure and 35.5dB IIP3. In the proposed LNA, active inductor circuit replaces the usual passive spiral inductor to keep the size of the chip area at 0.0004mm2. Such an LNA will be a better choice for high performance, fully integrated, low cost and low power RF receivers. Zasnova nizko šumnega ojačevalnika na osnovi aktivne dušilke s Silterra 130 nm CMOS tehnološkim procesom Izvleček: V članku je prikazan CMOS nizko šumni ojačevalnik (LNA) na osnovi aktivne dušilke za RF sprejemnike v ISM frekvenčnem območju 2,4 GHz. Predlagani LNA je sestavljen iz treh stopenj: ojačevalnik s skupnimi vrati, aktivna dušilka in izhodni ojačevalnik. LNA je načrtovan za Silterra 130-nm CMOS proces. Deluje pri napajalni napetosti 1,2 V, ima veliko ojačenje (S21) 33 dB in majhno povratno ojačenje (S12) 33,1 dB. Poraba moči znaša le 1,51 mW, šumno število ima 8.51 dB in IIP3 35,5 dB. Pri predlaganem LNA aktivna dušilka nadomešča običajno pasivno spiralno dušilko, s čimer dosežemo velikost vezja le 0,0004 mm2. Tak LNA bo boljša izbira za visokozmogljive v celoti integrirane nizkocenovne RF sprejemnike nizkih moči.

Modern Radio Frequency (RF) transceivers cannot be imagined without high-performance (Transmit/ R... more Modern Radio Frequency (RF) transceivers cannot be imagined without high-performance (Transmit/ Receive) T/R switch. Available T/R switches suffer mainly due to the lack of good trade-off among the performance parameters, where high isolation and low insertion loss are very essential. In this study, a T/R switch with high isolation and low insertion loss performance has been designed by using Silterra 0.13µm CMOS process for 2.4GHz ISM band RF transceivers. Transistor aspect ratio optimization, proper gate bias resistance, resistive body floating and active inductor-based parallel resonance techniques have been implemented to achieve better trade-off. The proposed T/R switch exhibits 0.85dB insertion loss and 45.17dB isolation in both transmit and receive modes. Moreover, it shows very competitive values of power handling capability (P1dB) and linearity (IIP3) which are 11.35dBm and 19.60dBm, respectively. Due to avoiding bulky inductor and capacitor, the proposed active inductor-based T/R switch became highly compact occupying only 0.003mm 2 of silicon space; which will further trim down the total cost of the transceiver. Therefore, the proposed active inductor-based T/R switch in 0.13µm CMOS process will be highly useful for the electronic industries where low-power, high-performance and compactness of devices are the crucial concerns.

Precise navigation is a vital need for many modern vehicular applications. The global positioning... more Precise navigation is a vital need for many modern vehicular applications. The global positioning system (GPS) cannot provide
continuous navigation information in urban areas. The widely used inertial navigation system (INS) can provide full vehicle state
at high rates. However, the accuracy diverges quickly in low cost microelectromechanical systems (MEMS) based INS due to bias,
drift, noise, and other errors. These errors can be corrected in a stationary state. But detecting stationary state is a challenging task.
A novel stationary state detection technique from the variation of acceleration, heading, and pitch and roll of an attitude heading
reference system (AHRS) built from the inertial measurement unit (IMU) sensors is proposed. Besides, the map matching (MM)
algorithm detects the intersections where the vehicle is likely to stop. Combining these two results, the stationary state is detected
with a smaller timing window of 3 s. A longer timing window of 5 s is used when the stationary state is detected only from the
AHRS. The experimental results show that the stationary state is correctly identified and the position error is reduced to 90% and
outperforms previously reported work. The proposed algorithm would help to reduce INS errors and enhance the performance of
the navigation system.

Fully integrated CMOS single pole double through (SPDT) Transmit/Receive (T/R) switch is an essen... more Fully integrated CMOS single pole double through (SPDT) Transmit/Receive (T/R) switch is an essential component of every compact transceiver for enabling sharing of a single antenna between its transmitter and receiver. The switch is expected to encompass very low insertion loss, relatively higher isolation with high power handling capability. But there is inevitable trade-off among the parameters of the switch which makes the design even more challenging at 2.4 GHz ISM band. This paper presents a bibliographical survey of the work published on improved performance of different switch topologies for 2.4 GHz ISM band transceiver applications. Different techniques reported in literatures for further improvements in the characteristics of CMOS switches are also highlighted. This review will serve as a comparative study and reference for the researchers in designing T/R switches for future 2.4 GHz ISM band applications.

A low-cost accident detection system utilizing cheap ADXL345 accelerometers and GPS receiver is p... more A low-cost accident detection system utilizing cheap ADXL345 accelerometers and GPS receiver is proposed in this communication. The accident detection algorithm was developed based on sudden deceleration. The double integration of the acceleration and heading from the tilt angles of accelerometers were used to determine the location. Kalman filter was utilized to correct the accumulated double integration errors with the trusted GPS data. The field tests demonstrated the correct functioning of the accident detection algorithm and location. The proposed lowcost system can save many lives by the automated accident detection and accurate location even during GPS outage.

This paper proposes a transmit/receive (T/R) nanoswitch in 130 nm CMOS technology for 2.4 GHz ISM... more This paper proposes a transmit/receive (T/R) nanoswitch in 130 nm CMOS technology for 2.4 GHz ISM band transceivers. It exhibits 1.03-dB insertion loss, 27.57-dB isolation and a power handling capacity (P1 dB) of 36.2-dBm. It dissipates only 6.87 µW power for 1.8/0 V control voltages and is capable of switching in 416.61 ps. Besides insertion loss and isolation of the nanoswitch is found to vary by 0.1 dB and 0.9 dB, respectively for a temperature change of 125 • C. Only the transistor W/L optimization and resistive body floating technique is used for such lucrative performances. Besides absence of bulky inductors and capacitors in the schematic circuit help to attain the smallest chip area of 0.0071 mm 2 which is the lowest ever reported in this frequency band. Therefore, simplicity and low chip area of the circuit trim down the cost of fabrication without compromising the performance issue.

The shift register is the heart of the current digital data storage system. Current trends of wir... more The shift register is the heart of the current digital data storage system. Current trends of wireless device designs are to balance the power consumption, cost and portability of the device. The worldwide research is giving emphasize on increasing the amount of memory at minimum possible space to reduce the overall size of the devices now a days. This paper reports a detailed survey on different types of shift registers in CMOS technology from the performance, design and application point of view. It also discusses the technologies available for the design of shift registers with their merits and demerits. This survey will act as a reference for the scientists to design the high-performance memory module.

Fully integrated CMOS band-pass filter is a prerequisite of all modern transceivers. The filters ... more Fully integrated CMOS band-pass filter is a prerequisite of all modern transceivers. The filters are expected to encompass very low power dissipation, relatively higher Q-factor with proper centre frequency tuning. But there is some trade off among the parameters. Conventional band-pass filters suffer from some inevitable drawbacks which are not prominent in CMOS Gm-C configuration. In this paper, a review on the advancement of Gm-C filter circuits, illustrated in different literatures, is discussed with their merits and demerits. This review will serve as a comparative studies and reference for the researchers in designing future high performance band-pass filters for wireless transceiver frontend applications.

Low noise and low Power transimpedance amplifiers (TIA) are essential modules for optical sensor ... more Low noise and low Power transimpedance amplifiers (TIA) are essential modules for optical sensor based systems. But low power and low noise TIAs are still a challenge for the scientists despite of rapid advances in complementary metal oxide semiconductor (CMOS) technology. This paper proposes a three-stage nested miller compensated (NMC) based design of low noise low power transimpedance amplifier for stable wideband operation. The circuit is designed in the 0.18µm CMOS technology by using Mentor Graphics environment. The simulation results show that the proposed TIA can operate at frequency 20 KHz and produces an output of 1.4265V for ±1.2 V input voltages dissipating only 2.9206 mW power at 27°C temperature. The complete layout of the TIA is only 0.005 µm 2 .This shunt-feedback TIA can be a better choice for high-resolution, low-to mid frequency applications.

IET Circuits, Devices & Systems, 2020

Electronics, 2019

Sensors, 2021

Diagnostics, 2021

Diagnistics, 2021

IEEE Access, 2021

Micro and Nanosystems, 2018

The shift register is a type of sequential logic circuit which is mostly used for storing digital... more The shift register is a type of sequential logic circuit which is mostly used for storing digital data or the transferring of data in the form of binary numbers in radio frequency identification (RFID) applications to improve the security of the system. A power-efficient shift register utilizing a new flip-flop with an implicit pulse-triggered structure is presented in this article. The proposed flip-flop has features of high performance and low power. It is composed of a sampling circuit implemented by five transistors, a C-element for rise and fall paths, and a keeper stage. The speed is enhanced by executing four clocked transistors together with a transition condition technique. The simulation result confirms that the proposed topology consumes the lowest amounts of power of 30.1997 and 22.7071 nW for parallel in –parallel out (PIPO) and serial in –serial out (SISO) shift register respectively covering 22 µm 2 chip area. The overall design consist of only 16 transistors and is simulated in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology with a 1.2 V power supply.