Marek Węgrzyn | University of Zielona Gora (original) (raw)

Papers by Marek Węgrzyn

Computers & Electrical Engineering, 2016

Extreme Learning Machine (ELM) proposes a non-iterative training method for Single Layer Feedforw... more Extreme Learning Machine (ELM) proposes a non-iterative training method for Single Layer Feedforward Neural Networks that provides an effective solution for classification and prediction problems. It s hardware implementation is an important step towards fast, accurate and reconfigurable embedded systems based on neural networks, allowing to extend the range of applications where neural networks can be used, especially where frequent and fast training, or even real-time training, is required. This work proposes three hardware architectures for on-chip ELM training computation and implementation, a sequential and two parallel. All three are implemented parameterizably on FPGA as an IP (Intellectual Property) core. Results describe performance, accuracy, resources and power consumption. The analysis is conducted parametrically varying the number of hidden neurons, number of training patterns and internal bit-length, providing a guideline on required resources and level of performance that an FPGA based ELM training can provide.

Design of Embedded Control Systems

This paper discusses how the FPGA architectures affect the implementation of Petri net specificat... more This paper discusses how the FPGA architectures affect the implementation of Petri net specifications. Taking in consideration the observations from that study, a method is developed for obtaining VHDL descriptions amenable to synthesis, and t ested against other standard methods of implementation. These results have relevance in the integration of access technologies to high speed telecommunication networks, where FPGAs are excellent implementation platforms.

Pomiary Automatyka Robotyka

This study provides a new class of controllers for freeflying space manipulators subject to unkno... more This study provides a new class of controllers for freeflying space manipulators subject to unknown undesirable disturbing forces exerted on the end-effector. Based on suitably defined taskspace non-singular terminal sliding manifold and the Lyapunov stability theory, we derive a class of estimated extended transposed Jacobian controllers which seem to be effective in counteracting the unstructured disturbing forces. The numerical computations which are carried out for a space manipulator consisting of a spacecraft propelled by eight thrusters and holonomic manipulator of three revolute kinematic pairs, illustrate the performance of the proposed controller.

ISIE '97 Proceeding of the IEEE International Symposium on Industrial Electronics

Page 1. Coloured Petri Net Model of Application Specific Logic Controller Programs Marek Wegrzyn,... more Page 1. Coloured Petri Net Model of Application Specific Logic Controller Programs Marek Wegrzyn, Pawel Wolanski, Prof Marian Adamski Department of Computer Engineering and Electronics Technical University of Zielona Gora SO. ...

IFAC Proceedings Volumes, 1997

An implemented design framework contains the Programmable Logic based synthesis of rule-based des... more An implemented design framework contains the Programmable Logic based synthesis of rule-based descriptions that are obtained from several specification models of Concurrent Controllers (for example: Control Interpreted Petri net, Grafcet or IEC 1131-3 Sequential Function Chart). The specification in the form of symbolic conditional decision rules is transformed into a format that is accepted by standard FPLD & FPGA simulators and synthesizers, for example OrCAD or VHDL. The Concurrent State Machine model of Logic Controller is verified using the well-developed Petri net theory. and then it is translated through automated processes into selected FPGA specification format, for example Xilinx netlist format (XNF).

IFAC Proceedings Volumes, 2000

In the paper a structured synthesis method based on the direct mapping of hierarchical interprete... more In the paper a structured synthesis method based on the direct mapping of hierarchical interpreted Petri nets into field programmable logic is presented. The described methodology is especially useful for designing of Industrial Application Specific Logic Controllers (ASLCs) with FPGA. The specification of the reactive system in the fonn of symbolic, if-then or if-then-else conditional decision rules is transfonned into a HDL format that is accepted by standard FPGA simulators and synthesis tools. The Concurrent State Machine model of Logic Controller is verified using the well-developed Petri net theory, and then it is translated through automated processes into selected FPGA specification format.

IFAC Proceedings Volumes, 2006

The method of partial reconfiguration of Compositional Microprogram Control Units implemented on ... more The method of partial reconfiguration of Compositional Microprogram Control Units implemented on FPGAs is proposed. The method is based on the swapping of the contcnt of Control Memory while the rest of the system is not modified. Such approach permits to decrease the si7.e of a bit-stream that is sent to the device. Therefore time needed for device configuration is shorter. Proposed solution is much more safe due to less errors that can occur during reconfiguration of FPGAs. An example of proposed method application is discussed. The n:searches conducted by authors have shown that proposed method permits to decrease the si7.e of a bit-stream that is sent to the device in comparison with traditional method even up to 95%.

IEEE Transactions on Industrial Informatics, 2016

Typically, hardware implemented neural networks are trained before implementation. Extreme Learni... more Typically, hardware implemented neural networks are trained before implementation. Extreme Learning Machine (ELM) is a non-iterative training method for Single Layer Feed Forward Neural Networks (SLFF-NN) well suited for hardware implementation. It provides fixed-time learning and simplifies retraining of a neural network once implemented, very important in applications demanding on-chip training. This work proposes the data flow of a software support tool in the design process of a hardware implementation of on-chip ELM learning for SLFF neural networks. The software tool allows the user to obtain the optimal definition of functional and hardware parameters for any application, and enables the user to interact throughout the design process. Combining, in a transparent way for the user, simulation and Xilinx synthesis tools, the tool recommends the optimal configuration, generating, finally, a synthesizable IP-core. As application, the FPGA implementation for real-time detection of brain areas in electrode positioning during a Deep Brain Stimulation (DBS) surgery is described. The generated IP-core can execute a peak of 95 ELM trainings per second on a lowcost Spartan 6 device, making possible its real-time use in this application.

IFAC-PapersOnLine, 2015

Abstract The paper presents a new concept of the selection of prime implicants in a two-level log... more Abstract The paper presents a new concept of the selection of prime implicants in a two-level logic minimization of Boolean functions. The method is based on the two-level minimization process of the Boolean functions, according to the Quine-McCluskey approach. Initially, the set of prime implicants for the logic function ought to be calculated. Next, the selection process is applied to achieve the minimal formula. Such an operation is a typical covering problem and in general case it has exponential computational complexity. In the paper we propose a new prime implicants selection method. An idea is based on the hypergraph theory. The prime implicants matrix (chart) is formed as a selection hypergraph. If the selection hyper-graph belongs to the Exact Transversal Hypergraph class ( xt-class ), the solution may be obtained in a polynomial time, which is not possible in a general case. The proposed method is illustrated by an example. All necessary steps will be shown in order to apply the proposed selection algorithm to minimize an exemplary Boolean function.

IFAC-PapersOnLine, 2015

Abstract A method is proposed for implementing Mealy FSMs logic circuits with embedded memory blo... more Abstract A method is proposed for implementing Mealy FSMs logic circuits with embedded memory blocks. The method is based on encoding of the rows of FSM structure table and replacement of logical conditions. Example of design and results of investigations are given. Our approach allows diminishing the number of LUTs in the block of RLC due to splitting the initial set of logical conditions. Also it results in the decrease of used EMBs for around 15% of standard benchmarks.

SPIE Proceedings, 2005

ABSTRACT

IFAC Proceedings Volumes, 2013

Abstract In the paper a method of using the Unified Modeling Language diagrams for specification ... more Abstract In the paper a method of using the Unified Modeling Language diagrams for specification of digital systems, especially logic controllers, is presented. The proposed method is based mainly on the UML state machine diagrams and uses Hierarchical Concurrent Finite State Machines (HCFSMs) as a temporary model. The paper shows a way to transform the UML diagrams to the form that is acceptable by reconfigurable FPGAs (Field Programmable Gate Arrays). The UML specification is used to generate an effective program in Hardware Description Languages (HDLs), especially Verilog.

Computers & Electrical Engineering, 2016

Extreme Learning Machine (ELM) proposes a non-iterative training method for Single Layer Feedforw... more Extreme Learning Machine (ELM) proposes a non-iterative training method for Single Layer Feedforward Neural Networks that provides an effective solution for classification and prediction problems. It s hardware implementation is an important step towards fast, accurate and reconfigurable embedded systems based on neural networks, allowing to extend the range of applications where neural networks can be used, especially where frequent and fast training, or even real-time training, is required. This work proposes three hardware architectures for on-chip ELM training computation and implementation, a sequential and two parallel. All three are implemented parameterizably on FPGA as an IP (Intellectual Property) core. Results describe performance, accuracy, resources and power consumption. The analysis is conducted parametrically varying the number of hidden neurons, number of training patterns and internal bit-length, providing a guideline on required resources and level of performance that an FPGA based ELM training can provide.

Design of Embedded Control Systems

This paper discusses how the FPGA architectures affect the implementation of Petri net specificat... more This paper discusses how the FPGA architectures affect the implementation of Petri net specifications. Taking in consideration the observations from that study, a method is developed for obtaining VHDL descriptions amenable to synthesis, and t ested against other standard methods of implementation. These results have relevance in the integration of access technologies to high speed telecommunication networks, where FPGAs are excellent implementation platforms.

Pomiary Automatyka Robotyka

This study provides a new class of controllers for freeflying space manipulators subject to unkno... more This study provides a new class of controllers for freeflying space manipulators subject to unknown undesirable disturbing forces exerted on the end-effector. Based on suitably defined taskspace non-singular terminal sliding manifold and the Lyapunov stability theory, we derive a class of estimated extended transposed Jacobian controllers which seem to be effective in counteracting the unstructured disturbing forces. The numerical computations which are carried out for a space manipulator consisting of a spacecraft propelled by eight thrusters and holonomic manipulator of three revolute kinematic pairs, illustrate the performance of the proposed controller.

ISIE '97 Proceeding of the IEEE International Symposium on Industrial Electronics

Page 1. Coloured Petri Net Model of Application Specific Logic Controller Programs Marek Wegrzyn,... more Page 1. Coloured Petri Net Model of Application Specific Logic Controller Programs Marek Wegrzyn, Pawel Wolanski, Prof Marian Adamski Department of Computer Engineering and Electronics Technical University of Zielona Gora SO. ...

IFAC Proceedings Volumes, 1997

An implemented design framework contains the Programmable Logic based synthesis of rule-based des... more An implemented design framework contains the Programmable Logic based synthesis of rule-based descriptions that are obtained from several specification models of Concurrent Controllers (for example: Control Interpreted Petri net, Grafcet or IEC 1131-3 Sequential Function Chart). The specification in the form of symbolic conditional decision rules is transformed into a format that is accepted by standard FPLD & FPGA simulators and synthesizers, for example OrCAD or VHDL. The Concurrent State Machine model of Logic Controller is verified using the well-developed Petri net theory. and then it is translated through automated processes into selected FPGA specification format, for example Xilinx netlist format (XNF).

IFAC Proceedings Volumes, 2000

In the paper a structured synthesis method based on the direct mapping of hierarchical interprete... more In the paper a structured synthesis method based on the direct mapping of hierarchical interpreted Petri nets into field programmable logic is presented. The described methodology is especially useful for designing of Industrial Application Specific Logic Controllers (ASLCs) with FPGA. The specification of the reactive system in the fonn of symbolic, if-then or if-then-else conditional decision rules is transfonned into a HDL format that is accepted by standard FPGA simulators and synthesis tools. The Concurrent State Machine model of Logic Controller is verified using the well-developed Petri net theory, and then it is translated through automated processes into selected FPGA specification format.

IFAC Proceedings Volumes, 2006

The method of partial reconfiguration of Compositional Microprogram Control Units implemented on ... more The method of partial reconfiguration of Compositional Microprogram Control Units implemented on FPGAs is proposed. The method is based on the swapping of the contcnt of Control Memory while the rest of the system is not modified. Such approach permits to decrease the si7.e of a bit-stream that is sent to the device. Therefore time needed for device configuration is shorter. Proposed solution is much more safe due to less errors that can occur during reconfiguration of FPGAs. An example of proposed method application is discussed. The n:searches conducted by authors have shown that proposed method permits to decrease the si7.e of a bit-stream that is sent to the device in comparison with traditional method even up to 95%.

IEEE Transactions on Industrial Informatics, 2016

Typically, hardware implemented neural networks are trained before implementation. Extreme Learni... more Typically, hardware implemented neural networks are trained before implementation. Extreme Learning Machine (ELM) is a non-iterative training method for Single Layer Feed Forward Neural Networks (SLFF-NN) well suited for hardware implementation. It provides fixed-time learning and simplifies retraining of a neural network once implemented, very important in applications demanding on-chip training. This work proposes the data flow of a software support tool in the design process of a hardware implementation of on-chip ELM learning for SLFF neural networks. The software tool allows the user to obtain the optimal definition of functional and hardware parameters for any application, and enables the user to interact throughout the design process. Combining, in a transparent way for the user, simulation and Xilinx synthesis tools, the tool recommends the optimal configuration, generating, finally, a synthesizable IP-core. As application, the FPGA implementation for real-time detection of brain areas in electrode positioning during a Deep Brain Stimulation (DBS) surgery is described. The generated IP-core can execute a peak of 95 ELM trainings per second on a lowcost Spartan 6 device, making possible its real-time use in this application.

IFAC-PapersOnLine, 2015

Abstract The paper presents a new concept of the selection of prime implicants in a two-level log... more Abstract The paper presents a new concept of the selection of prime implicants in a two-level logic minimization of Boolean functions. The method is based on the two-level minimization process of the Boolean functions, according to the Quine-McCluskey approach. Initially, the set of prime implicants for the logic function ought to be calculated. Next, the selection process is applied to achieve the minimal formula. Such an operation is a typical covering problem and in general case it has exponential computational complexity. In the paper we propose a new prime implicants selection method. An idea is based on the hypergraph theory. The prime implicants matrix (chart) is formed as a selection hypergraph. If the selection hyper-graph belongs to the Exact Transversal Hypergraph class ( xt-class ), the solution may be obtained in a polynomial time, which is not possible in a general case. The proposed method is illustrated by an example. All necessary steps will be shown in order to apply the proposed selection algorithm to minimize an exemplary Boolean function.

IFAC-PapersOnLine, 2015

Abstract A method is proposed for implementing Mealy FSMs logic circuits with embedded memory blo... more Abstract A method is proposed for implementing Mealy FSMs logic circuits with embedded memory blocks. The method is based on encoding of the rows of FSM structure table and replacement of logical conditions. Example of design and results of investigations are given. Our approach allows diminishing the number of LUTs in the block of RLC due to splitting the initial set of logical conditions. Also it results in the decrease of used EMBs for around 15% of standard benchmarks.

SPIE Proceedings, 2005

ABSTRACT

IFAC Proceedings Volumes, 2013

Abstract In the paper a method of using the Unified Modeling Language diagrams for specification ... more Abstract In the paper a method of using the Unified Modeling Language diagrams for specification of digital systems, especially logic controllers, is presented. The proposed method is based mainly on the UML state machine diagrams and uses Hierarchical Concurrent Finite State Machines (HCFSMs) as a temporary model. The paper shows a way to transform the UML diagrams to the form that is acceptable by reconfigurable FPGAs (Field Programmable Gate Arrays). The UML specification is used to generate an effective program in Hardware Description Languages (HDLs), especially Verilog.