clang: lib/Sema/SemaRISCV.cpp Source File (original) (raw)

64#define DECL_SIGNATURE_TABLE

65#include "clang/Basic/riscv_vector_builtin_sema.inc"

66#undef DECL_SIGNATURE_TABLE

67};

70#define DECL_SIGNATURE_TABLE

71#include "clang/Basic/riscv_sifive_vector_builtin_sema.inc"

72#undef DECL_SIGNATURE_TABLE

73};

76#define DECL_SIGNATURE_TABLE

77#include "clang/Basic/riscv_andes_vector_builtin_sema.inc"

78#undef DECL_SIGNATURE_TABLE

79};

82#define DECL_INTRINSIC_RECORDS

83#include "clang/Basic/riscv_vector_builtin_sema.inc"

84#undef DECL_INTRINSIC_RECORDS

85};

88#define DECL_INTRINSIC_RECORDS

89#include "clang/Basic/riscv_sifive_vector_builtin_sema.inc"

90#undef DECL_INTRINSIC_RECORDS

91};

94#define DECL_INTRINSIC_RECORDS

95#include "clang/Basic/riscv_andes_vector_builtin_sema.inc"

96#undef DECL_INTRINSIC_RECORDS

97};

102 switch (K) {

103 case IntrinsicKind::RVV:

105 case IntrinsicKind::SIFIVE_VECTOR:

107 case IntrinsicKind::ANDES_VECTOR:

109 }

110 llvm_unreachable("Unhandled IntrinsicKind");

111}

115 switch (Type->getScalarType()) {

117 QT = Context.VoidTy;

118 break;

120 QT = Context.getSizeType();

121 break;

123 QT = Context.getPointerDiffType();

124 break;

126 QT = Context.UnsignedLongTy;

127 break;

129 QT = Context.LongTy;

130 break;

132 QT = Context.BoolTy;

133 break;

135 QT = Context.getIntTypeForBitwidth(Type->getElementBitwidth(), true);

136 break;

138 QT = Context.getIntTypeForBitwidth(Type->getElementBitwidth(), false);

139 break;

141 QT = Context.BFloat16Ty;

142 break;

144 switch (Type->getElementBitwidth()) {

145 case 64:

146 QT = Context.DoubleTy;

147 break;

148 case 32:

149 QT = Context.FloatTy;

150 break;

151 case 16:

152 QT = Context.Float16Ty;

153 break;

154 default:

155 llvm_unreachable("Unsupported floating point width.");

156 }

157 break;

160 llvm_unreachable("Unhandled type.");

161 }

162 if (Type->isVector()) {

163 if (Type->isTuple())

164 QT = Context.getScalableVectorType(QT, *Type->getScale(), Type->getNF());

165 else

166 QT = Context.getScalableVectorType(QT, *Type->getScale());

167 }

168

169 if (Type->isConstant())

170 QT = Context.getConstType(QT);

171

172

173 if (Type->isPointer())

174 QT = Context.getPointerType(QT);

175

176 return QT;

177}

388 IntrinsicList.push_back({BuiltinName, Record.RequiredExtensions, Signature});

499 return std::make_unique(S);

500}

504

505

508 return false;

509

510

511 if (SemaRef.BuiltinConstantArg(TheCall, ArgNum, Result))

512 return true;

513

514 int64_t Val = Result.getSExtValue();

515 if ((Val >= 0 && Val <= 3) || (Val >= 5 && Val <= 7))

516 return false;

517

518 return Diag(TheCall->getBeginLoc(), diag::err_riscv_builtin_invalid_lmul)

520}

523 llvm::StringMap &FunctionFeatureMap,

525 int EGW) {

526 assert((EGW == 128 || EGW == 256) && "EGW can only be 128 or 256 bits");

527

528

532 unsigned MinElemCount = Info.EC.getKnownMinValue();

533

534 unsigned EGS = EGW / ElemSize;

535

536

537 if (EGS <= MinElemCount)

538 return false;

539

540

541 assert(EGS % MinElemCount == 0);

542 unsigned VScaleFactor = EGS / MinElemCount;

543

544 unsigned MinRequiredVLEN = VScaleFactor * llvm::RISCV::RVVBitsPerBlock;

545 std::string RequiredExt = "zvl" + std::to_string(MinRequiredVLEN) + "b";

546 if (!TI.hasFeature(RequiredExt) && !FunctionFeatureMap.lookup(RequiredExt))

548 diag::err_riscv_type_requires_extension)

549 << Type << RequiredExt;

550

551 return false;

552}

555 unsigned BuiltinID,

559 llvm::StringMap FunctionFeatureMap;

560 Context.getFunctionFeatureMap(FunctionFeatureMap, FD);

561

563 StringRef FeaturesStr = A->getFeaturesStr();

565 FeaturesStr.split(RequiredFeatures, ',');

566 for (auto RF : RequiredFeatures)

567 if (!TI.hasFeature(RF) && !FunctionFeatureMap.lookup(RF))

569 diag::err_riscv_builtin_requires_extension)

570 << true << TheCall->getSourceRange() << RF;

571 }

572

573

574

575 switch (BuiltinID) {

576 default:

577 break;

578 case RISCVVector::BI__builtin_rvv_vmulhsu_vv:

579 case RISCVVector::BI__builtin_rvv_vmulhsu_vx:

580 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_tu:

581 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_tu:

582 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_m:

583 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_m:

584 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_mu:

585 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_mu:

586 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_tum:

587 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_tum:

588 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_tumu:

589 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_tumu:

590 case RISCVVector::BI__builtin_rvv_vmulhu_vv:

591 case RISCVVector::BI__builtin_rvv_vmulhu_vx:

592 case RISCVVector::BI__builtin_rvv_vmulhu_vv_tu:

593 case RISCVVector::BI__builtin_rvv_vmulhu_vx_tu:

594 case RISCVVector::BI__builtin_rvv_vmulhu_vv_m:

595 case RISCVVector::BI__builtin_rvv_vmulhu_vx_m:

596 case RISCVVector::BI__builtin_rvv_vmulhu_vv_mu:

597 case RISCVVector::BI__builtin_rvv_vmulhu_vx_mu:

598 case RISCVVector::BI__builtin_rvv_vmulhu_vv_tum:

599 case RISCVVector::BI__builtin_rvv_vmulhu_vx_tum:

600 case RISCVVector::BI__builtin_rvv_vmulhu_vv_tumu:

601 case RISCVVector::BI__builtin_rvv_vmulhu_vx_tumu:

602 case RISCVVector::BI__builtin_rvv_vmulh_vv:

603 case RISCVVector::BI__builtin_rvv_vmulh_vx:

604 case RISCVVector::BI__builtin_rvv_vmulh_vv_tu:

605 case RISCVVector::BI__builtin_rvv_vmulh_vx_tu:

606 case RISCVVector::BI__builtin_rvv_vmulh_vv_m:

607 case RISCVVector::BI__builtin_rvv_vmulh_vx_m:

608 case RISCVVector::BI__builtin_rvv_vmulh_vv_mu:

609 case RISCVVector::BI__builtin_rvv_vmulh_vx_mu:

610 case RISCVVector::BI__builtin_rvv_vmulh_vv_tum:

611 case RISCVVector::BI__builtin_rvv_vmulh_vx_tum:

612 case RISCVVector::BI__builtin_rvv_vmulh_vv_tumu:

613 case RISCVVector::BI__builtin_rvv_vmulh_vx_tumu:

614 case RISCVVector::BI__builtin_rvv_vsmul_vv:

615 case RISCVVector::BI__builtin_rvv_vsmul_vx:

616 case RISCVVector::BI__builtin_rvv_vsmul_vv_tu:

617 case RISCVVector::BI__builtin_rvv_vsmul_vx_tu:

618 case RISCVVector::BI__builtin_rvv_vsmul_vv_m:

619 case RISCVVector::BI__builtin_rvv_vsmul_vx_m:

620 case RISCVVector::BI__builtin_rvv_vsmul_vv_mu:

621 case RISCVVector::BI__builtin_rvv_vsmul_vx_mu:

622 case RISCVVector::BI__builtin_rvv_vsmul_vv_tum:

623 case RISCVVector::BI__builtin_rvv_vsmul_vx_tum:

624 case RISCVVector::BI__builtin_rvv_vsmul_vv_tumu:

625 case RISCVVector::BI__builtin_rvv_vsmul_vx_tumu: {

628

630 !FunctionFeatureMap.lookup("v"))

632 diag::err_riscv_builtin_requires_extension)

633 << true << TheCall->getSourceRange() << "v";

634

635 break;

636 }

637 }

638

639 auto CheckVSetVL = [&](unsigned SEWOffset, unsigned LMULOffset) -> bool {

641 llvm::StringMap FunctionFeatureMap;

642 Context.getFunctionFeatureMap(FunctionFeatureMap, FD);

643 llvm::APSInt SEWResult;

644 llvm::APSInt LMULResult;

645 if (SemaRef.BuiltinConstantArg(TheCall, SEWOffset, SEWResult) ||

646 SemaRef.BuiltinConstantArg(TheCall, LMULOffset, LMULResult))

647 return true;

648 int SEWValue = SEWResult.getSExtValue();

649 int LMULValue = LMULResult.getSExtValue();

650 if (((SEWValue == 0 && LMULValue == 5) ||

651 (SEWValue == 1 && LMULValue == 6) ||

652 (SEWValue == 2 && LMULValue == 7) ||

653 SEWValue == 3) &&

655 !FunctionFeatureMap.lookup("zve64x"))

657 diag::err_riscv_builtin_requires_extension)

658 << true << TheCall->getSourceRange() << "zve64x";

659 return SemaRef.BuiltinConstantArgRange(TheCall, SEWOffset, 0, 3) ||

661 };

662 switch (BuiltinID) {

663 case RISCVVector::BI__builtin_rvv_vsetvli:

664 return CheckVSetVL(1, 2);

665 case RISCVVector::BI__builtin_rvv_vsetvlimax:

666 return CheckVSetVL(0, 1);

667 case RISCVVector::BI__builtin_rvv_sf_vsettnt:

668 case RISCVVector::BI__builtin_rvv_sf_vsettm:

669 case RISCVVector::BI__builtin_rvv_sf_vsettn:

670 case RISCVVector::BI__builtin_rvv_sf_vsettk:

671 return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 3) ||

672 SemaRef.BuiltinConstantArgRange(TheCall, 2, 1, 3);

673 case RISCVVector::BI__builtin_rvv_sf_mm_f_f_w1:

674 case RISCVVector::BI__builtin_rvv_sf_mm_f_f_w2:

675 case RISCVVector::BI__builtin_rvv_sf_mm_e5m2_e4m3_w4:

676 case RISCVVector::BI__builtin_rvv_sf_mm_e5m2_e5m2_w4:

677 case RISCVVector::BI__builtin_rvv_sf_mm_e4m3_e4m3_w4:

678 case RISCVVector::BI__builtin_rvv_sf_mm_e4m3_e5m2_w4:

679 case RISCVVector::BI__builtin_rvv_sf_mm_u_u_w4:

680 case RISCVVector::BI__builtin_rvv_sf_mm_u_s_w4:

681 case RISCVVector::BI__builtin_rvv_sf_mm_s_u_w4:

682 case RISCVVector::BI__builtin_rvv_sf_mm_s_s_w4: {

685 SemaRef.Context.getBuiltinVectorTypeInfo(

689

690

693 return false;

694

695

696 if (SemaRef.BuiltinConstantArg(TheCall, 0, Result))

697 return true;

698

699

700

701

702 if ((BuiltinID == RISCVVector::BI__builtin_rvv_sf_mm_f_f_w1 &&

703 EltSize == 64) ||

704 (BuiltinID == RISCVVector::BI__builtin_rvv_sf_mm_f_f_w2 &&

705 EltSize == 32))

706 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 15) ||

707 SemaRef.BuiltinConstantArgMultiple(TheCall, 0, 2);

708 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 15) ||

709 SemaRef.BuiltinConstantArgMultiple(TheCall, 0, 4);

710 }

711 case RISCVVector::BI__builtin_rvv_sf_vtzero_t: {

712 llvm::APSInt Log2SEWResult;

713 llvm::APSInt TWidenResult;

714 if (SemaRef.BuiltinConstantArg(TheCall, 3, Log2SEWResult) ||

715 SemaRef.BuiltinConstantArg(TheCall, 4, TWidenResult))

716 return true;

717

718 int Log2SEW = Log2SEWResult.getSExtValue();

719 int TWiden = TWidenResult.getSExtValue();

720

721

722 if (SemaRef.BuiltinConstantArgRange(TheCall, 3, 3, 6))

723 return true;

724

725

726 if (TWiden != 1 && TWiden != 2 && TWiden != 4)

728 diag::err_riscv_builtin_invalid_twiden);

729

730 int TEW = (1 << Log2SEW) * TWiden;

731

732

733

734

735 if (SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 15))

736 return true;

737 if (TEW == 16 || TEW == 64)

738 return SemaRef.BuiltinConstantArgMultiple(TheCall, 0, 2);

739 return SemaRef.BuiltinConstantArgMultiple(TheCall, 0, 4);

740 }

741 case RISCVVector::BI__builtin_rvv_vget_v: {

748 unsigned MaxIndex;

749 if (VecInfo.NumVectors != 1)

751 else

752 MaxIndex = (VecInfo.EC.getKnownMinValue() * VecInfo.NumVectors) /

753 (ResVecInfo.EC.getKnownMinValue() * ResVecInfo.NumVectors);

754 return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, MaxIndex - 1);

755 }

756 case RISCVVector::BI__builtin_rvv_vset_v: {

763 unsigned MaxIndex;

764 if (ResVecInfo.NumVectors != 1)

766 else

767 MaxIndex = (ResVecInfo.EC.getKnownMinValue() * ResVecInfo.NumVectors) /

768 (VecInfo.EC.getKnownMinValue() * VecInfo.NumVectors);

769 return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, MaxIndex - 1);

770 }

771

772 case RISCVVector::BI__builtin_rvv_vaeskf1_vi_tu:

773 case RISCVVector::BI__builtin_rvv_vaeskf2_vi_tu:

774 case RISCVVector::BI__builtin_rvv_vaeskf2_vi:

775 case RISCVVector::BI__builtin_rvv_vsm4k_vi_tu: {

779 Arg0Type, 128) ||

781 Arg1Type, 128) ||

782 SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 31);

783 }

784 case RISCVVector::BI__builtin_rvv_vsm3c_vi_tu:

785 case RISCVVector::BI__builtin_rvv_vsm3c_vi: {

788 Arg0Type, 256) ||

789 SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 31);

790 }

791 case RISCVVector::BI__builtin_rvv_vaeskf1_vi:

792 case RISCVVector::BI__builtin_rvv_vsm4k_vi: {

795 Arg0Type, 128) ||

796 SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 31);

797 }

798 case RISCVVector::BI__builtin_rvv_vaesdf_vv:

799 case RISCVVector::BI__builtin_rvv_vaesdf_vs:

800 case RISCVVector::BI__builtin_rvv_vaesdm_vv:

801 case RISCVVector::BI__builtin_rvv_vaesdm_vs:

802 case RISCVVector::BI__builtin_rvv_vaesef_vv:

803 case RISCVVector::BI__builtin_rvv_vaesef_vs:

804 case RISCVVector::BI__builtin_rvv_vaesem_vv:

805 case RISCVVector::BI__builtin_rvv_vaesem_vs:

806 case RISCVVector::BI__builtin_rvv_vaesz_vs:

807 case RISCVVector::BI__builtin_rvv_vsm4r_vv:

808 case RISCVVector::BI__builtin_rvv_vsm4r_vs:

809 case RISCVVector::BI__builtin_rvv_vaesdf_vv_tu:

810 case RISCVVector::BI__builtin_rvv_vaesdf_vs_tu:

811 case RISCVVector::BI__builtin_rvv_vaesdm_vv_tu:

812 case RISCVVector::BI__builtin_rvv_vaesdm_vs_tu:

813 case RISCVVector::BI__builtin_rvv_vaesef_vv_tu:

814 case RISCVVector::BI__builtin_rvv_vaesef_vs_tu:

815 case RISCVVector::BI__builtin_rvv_vaesem_vv_tu:

816 case RISCVVector::BI__builtin_rvv_vaesem_vs_tu:

817 case RISCVVector::BI__builtin_rvv_vaesz_vs_tu:

818 case RISCVVector::BI__builtin_rvv_vsm4r_vv_tu:

819 case RISCVVector::BI__builtin_rvv_vsm4r_vs_tu: {

823 Arg0Type, 128) ||

825 Arg1Type, 128);

826 }

827 case RISCVVector::BI__builtin_rvv_vsha2ch_vv:

828 case RISCVVector::BI__builtin_rvv_vsha2cl_vv:

829 case RISCVVector::BI__builtin_rvv_vsha2ms_vv:

830 case RISCVVector::BI__builtin_rvv_vsha2ch_vv_tu:

831 case RISCVVector::BI__builtin_rvv_vsha2cl_vv_tu:

832 case RISCVVector::BI__builtin_rvv_vsha2ms_vv_tu: {

837 Context.getBuiltinVectorTypeInfo(Arg0Type->castAs<BuiltinType>());

838 uint64_t ElemSize = Context.getTypeSize(Info.ElementType);

839 if (ElemSize == 64 && !TI.hasFeature("zvknhb") &&

840 !FunctionFeatureMap.lookup("zvknhb"))

842 diag::err_riscv_builtin_requires_extension)

843 << true << TheCall->getSourceRange() << "zvknhb";

844

845 if (!TI.hasFeature("zvknha") && !FunctionFeatureMap.lookup("zvknha") &&

846 !TI.hasFeature("zvknhb") && !FunctionFeatureMap.lookup("zvknhb"))

848 diag::err_riscv_builtin_requires_extension)

849 << true << TheCall->getSourceRange()

850 << "zvknha or zvknhb";

851

853 Arg0Type, ElemSize * 4) ||

855 Arg1Type, ElemSize * 4) ||

857 Arg2Type, ElemSize * 4);

858 }

859

860 case RISCVVector::BI__builtin_rvv_sf_vc_i_se:

861

862 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 3) ||

863 SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 31) ||

864 SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 31) ||

865 SemaRef.BuiltinConstantArgRange(TheCall, 3, -16, 15) ||

867 case RISCVVector::BI__builtin_rvv_sf_vc_iv_se:

868

869 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 3) ||

870 SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 31) ||

871 SemaRef.BuiltinConstantArgRange(TheCall, 3, -16, 15);

872 case RISCVVector::BI__builtin_rvv_sf_vc_v_i:

873 case RISCVVector::BI__builtin_rvv_sf_vc_v_i_se:

874

875 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 3) ||

876 SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 31) ||

877 SemaRef.BuiltinConstantArgRange(TheCall, 2, -16, 15);

878 case RISCVVector::BI__builtin_rvv_sf_vc_v_iv:

879 case RISCVVector::BI__builtin_rvv_sf_vc_v_iv_se:

880

881 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 3) ||

882 SemaRef.BuiltinConstantArgRange(TheCall, 2, -16, 15);

883 case RISCVVector::BI__builtin_rvv_sf_vc_ivv_se:

884 case RISCVVector::BI__builtin_rvv_sf_vc_ivw_se:

885 case RISCVVector::BI__builtin_rvv_sf_vc_v_ivv:

886 case RISCVVector::BI__builtin_rvv_sf_vc_v_ivw:

887 case RISCVVector::BI__builtin_rvv_sf_vc_v_ivv_se:

888 case RISCVVector::BI__builtin_rvv_sf_vc_v_ivw_se:

889

890 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 3) ||

891 SemaRef.BuiltinConstantArgRange(TheCall, 3, -16, 15);

892 case RISCVVector::BI__builtin_rvv_sf_vc_x_se:

893

894 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 3) ||

895 SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 31) ||

896 SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 31) ||

898 case RISCVVector::BI__builtin_rvv_sf_vc_xv_se:

899 case RISCVVector::BI__builtin_rvv_sf_vc_vv_se:

900

901 case RISCVVector::BI__builtin_rvv_sf_vc_v_x:

902 case RISCVVector::BI__builtin_rvv_sf_vc_v_x_se:

903

904 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 3) ||

905 SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 31);

906 case RISCVVector::BI__builtin_rvv_sf_vc_vvv_se:

907 case RISCVVector::BI__builtin_rvv_sf_vc_xvv_se:

908 case RISCVVector::BI__builtin_rvv_sf_vc_vvw_se:

909 case RISCVVector::BI__builtin_rvv_sf_vc_xvw_se:

910

911 case RISCVVector::BI__builtin_rvv_sf_vc_v_xv:

912 case RISCVVector::BI__builtin_rvv_sf_vc_v_vv:

913 case RISCVVector::BI__builtin_rvv_sf_vc_v_xv_se:

914 case RISCVVector::BI__builtin_rvv_sf_vc_v_vv_se:

915

916 case RISCVVector::BI__builtin_rvv_sf_vc_v_xvv:

917 case RISCVVector::BI__builtin_rvv_sf_vc_v_vvv:

918 case RISCVVector::BI__builtin_rvv_sf_vc_v_xvw:

919 case RISCVVector::BI__builtin_rvv_sf_vc_v_vvw:

920 case RISCVVector::BI__builtin_rvv_sf_vc_v_xvv_se:

921 case RISCVVector::BI__builtin_rvv_sf_vc_v_vvv_se:

922 case RISCVVector::BI__builtin_rvv_sf_vc_v_xvw_se:

923 case RISCVVector::BI__builtin_rvv_sf_vc_v_vvw_se:

924

925 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 3);

926 case RISCVVector::BI__builtin_rvv_sf_vc_fv_se:

927

928 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 1) ||

929 SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 31);

930 case RISCVVector::BI__builtin_rvv_sf_vc_fvv_se:

931 case RISCVVector::BI__builtin_rvv_sf_vc_fvw_se:

932 case RISCVVector::BI__builtin_rvv_sf_vc_v_fvv:

933 case RISCVVector::BI__builtin_rvv_sf_vc_v_fvw:

934 case RISCVVector::BI__builtin_rvv_sf_vc_v_fvv_se:

935 case RISCVVector::BI__builtin_rvv_sf_vc_v_fvw_se:

936

937 case RISCVVector::BI__builtin_rvv_sf_vc_v_fv:

938 case RISCVVector::BI__builtin_rvv_sf_vc_v_fv_se:

939

940 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 1);

941

942 case RISCV::BI__builtin_riscv_aes32dsi:

943 case RISCV::BI__builtin_riscv_aes32dsmi:

944 case RISCV::BI__builtin_riscv_aes32esi:

945 case RISCV::BI__builtin_riscv_aes32esmi:

946 case RISCV::BI__builtin_riscv_sm4ks:

947 case RISCV::BI__builtin_riscv_sm4ed:

948 return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 3);

949

950 case RISCV::BI__builtin_riscv_aes64ks1i:

951 return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 10);

952

953 case RISCVVector::BI__builtin_rvv_vaaddu_vv:

954 case RISCVVector::BI__builtin_rvv_vaaddu_vx:

955 case RISCVVector::BI__builtin_rvv_vaadd_vv:

956 case RISCVVector::BI__builtin_rvv_vaadd_vx:

957 case RISCVVector::BI__builtin_rvv_vasubu_vv:

958 case RISCVVector::BI__builtin_rvv_vasubu_vx:

959 case RISCVVector::BI__builtin_rvv_vasub_vv:

960 case RISCVVector::BI__builtin_rvv_vasub_vx:

961 case RISCVVector::BI__builtin_rvv_vsmul_vv:

962 case RISCVVector::BI__builtin_rvv_vsmul_vx:

963 case RISCVVector::BI__builtin_rvv_vssra_vv:

964 case RISCVVector::BI__builtin_rvv_vssra_vx:

965 case RISCVVector::BI__builtin_rvv_vssrl_vv:

966 case RISCVVector::BI__builtin_rvv_vssrl_vx:

967 case RISCVVector::BI__builtin_rvv_vnclip_wv:

968 case RISCVVector::BI__builtin_rvv_vnclip_wx:

969 case RISCVVector::BI__builtin_rvv_vnclipu_wv:

970 case RISCVVector::BI__builtin_rvv_vnclipu_wx:

971 return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 3);

972 case RISCVVector::BI__builtin_rvv_vaaddu_vv_tu:

973 case RISCVVector::BI__builtin_rvv_vaaddu_vx_tu:

974 case RISCVVector::BI__builtin_rvv_vaadd_vv_tu:

975 case RISCVVector::BI__builtin_rvv_vaadd_vx_tu:

976 case RISCVVector::BI__builtin_rvv_vasubu_vv_tu:

977 case RISCVVector::BI__builtin_rvv_vasubu_vx_tu:

978 case RISCVVector::BI__builtin_rvv_vasub_vv_tu:

979 case RISCVVector::BI__builtin_rvv_vasub_vx_tu:

980 case RISCVVector::BI__builtin_rvv_vsmul_vv_tu:

981 case RISCVVector::BI__builtin_rvv_vsmul_vx_tu:

982 case RISCVVector::BI__builtin_rvv_vssra_vv_tu:

983 case RISCVVector::BI__builtin_rvv_vssra_vx_tu:

984 case RISCVVector::BI__builtin_rvv_vssrl_vv_tu:

985 case RISCVVector::BI__builtin_rvv_vssrl_vx_tu:

986 case RISCVVector::BI__builtin_rvv_vnclip_wv_tu:

987 case RISCVVector::BI__builtin_rvv_vnclip_wx_tu:

988 case RISCVVector::BI__builtin_rvv_vnclipu_wv_tu:

989 case RISCVVector::BI__builtin_rvv_vnclipu_wx_tu:

990 case RISCVVector::BI__builtin_rvv_vaaddu_vv_m:

991 case RISCVVector::BI__builtin_rvv_vaaddu_vx_m:

992 case RISCVVector::BI__builtin_rvv_vaadd_vv_m:

993 case RISCVVector::BI__builtin_rvv_vaadd_vx_m:

994 case RISCVVector::BI__builtin_rvv_vasubu_vv_m:

995 case RISCVVector::BI__builtin_rvv_vasubu_vx_m:

996 case RISCVVector::BI__builtin_rvv_vasub_vv_m:

997 case RISCVVector::BI__builtin_rvv_vasub_vx_m:

998 case RISCVVector::BI__builtin_rvv_vsmul_vv_m:

999 case RISCVVector::BI__builtin_rvv_vsmul_vx_m:

1000 case RISCVVector::BI__builtin_rvv_vssra_vv_m:

1001 case RISCVVector::BI__builtin_rvv_vssra_vx_m:

1002 case RISCVVector::BI__builtin_rvv_vssrl_vv_m:

1003 case RISCVVector::BI__builtin_rvv_vssrl_vx_m:

1004 case RISCVVector::BI__builtin_rvv_vnclip_wv_m:

1005 case RISCVVector::BI__builtin_rvv_vnclip_wx_m:

1006 case RISCVVector::BI__builtin_rvv_vnclipu_wv_m:

1007 case RISCVVector::BI__builtin_rvv_vnclipu_wx_m:

1008 return SemaRef.BuiltinConstantArgRange(TheCall, 3, 0, 3);

1009 case RISCVVector::BI__builtin_rvv_vaaddu_vv_tum:

1010 case RISCVVector::BI__builtin_rvv_vaaddu_vv_tumu:

1011 case RISCVVector::BI__builtin_rvv_vaaddu_vv_mu:

1012 case RISCVVector::BI__builtin_rvv_vaaddu_vx_tum:

1013 case RISCVVector::BI__builtin_rvv_vaaddu_vx_tumu:

1014 case RISCVVector::BI__builtin_rvv_vaaddu_vx_mu:

1015 case RISCVVector::BI__builtin_rvv_vaadd_vv_tum:

1016 case RISCVVector::BI__builtin_rvv_vaadd_vv_tumu:

1017 case RISCVVector::BI__builtin_rvv_vaadd_vv_mu:

1018 case RISCVVector::BI__builtin_rvv_vaadd_vx_tum:

1019 case RISCVVector::BI__builtin_rvv_vaadd_vx_tumu:

1020 case RISCVVector::BI__builtin_rvv_vaadd_vx_mu:

1021 case RISCVVector::BI__builtin_rvv_vasubu_vv_tum:

1022 case RISCVVector::BI__builtin_rvv_vasubu_vv_tumu:

1023 case RISCVVector::BI__builtin_rvv_vasubu_vv_mu:

1024 case RISCVVector::BI__builtin_rvv_vasubu_vx_tum:

1025 case RISCVVector::BI__builtin_rvv_vasubu_vx_tumu:

1026 case RISCVVector::BI__builtin_rvv_vasubu_vx_mu:

1027 case RISCVVector::BI__builtin_rvv_vasub_vv_tum:

1028 case RISCVVector::BI__builtin_rvv_vasub_vv_tumu:

1029 case RISCVVector::BI__builtin_rvv_vasub_vv_mu:

1030 case RISCVVector::BI__builtin_rvv_vasub_vx_tum:

1031 case RISCVVector::BI__builtin_rvv_vasub_vx_tumu:

1032 case RISCVVector::BI__builtin_rvv_vasub_vx_mu:

1033 case RISCVVector::BI__builtin_rvv_vsmul_vv_mu:

1034 case RISCVVector::BI__builtin_rvv_vsmul_vx_mu:

1035 case RISCVVector::BI__builtin_rvv_vssra_vv_mu:

1036 case RISCVVector::BI__builtin_rvv_vssra_vx_mu:

1037 case RISCVVector::BI__builtin_rvv_vssrl_vv_mu:

1038 case RISCVVector::BI__builtin_rvv_vssrl_vx_mu:

1039 case RISCVVector::BI__builtin_rvv_vnclip_wv_mu:

1040 case RISCVVector::BI__builtin_rvv_vnclip_wx_mu:

1041 case RISCVVector::BI__builtin_rvv_vnclipu_wv_mu:

1042 case RISCVVector::BI__builtin_rvv_vnclipu_wx_mu:

1043 case RISCVVector::BI__builtin_rvv_vsmul_vv_tum:

1044 case RISCVVector::BI__builtin_rvv_vsmul_vx_tum:

1045 case RISCVVector::BI__builtin_rvv_vssra_vv_tum:

1046 case RISCVVector::BI__builtin_rvv_vssra_vx_tum:

1047 case RISCVVector::BI__builtin_rvv_vssrl_vv_tum:

1048 case RISCVVector::BI__builtin_rvv_vssrl_vx_tum:

1049 case RISCVVector::BI__builtin_rvv_vnclip_wv_tum:

1050 case RISCVVector::BI__builtin_rvv_vnclip_wx_tum:

1051 case RISCVVector::BI__builtin_rvv_vnclipu_wv_tum:

1052 case RISCVVector::BI__builtin_rvv_vnclipu_wx_tum:

1053 case RISCVVector::BI__builtin_rvv_vsmul_vv_tumu:

1054 case RISCVVector::BI__builtin_rvv_vsmul_vx_tumu:

1055 case RISCVVector::BI__builtin_rvv_vssra_vv_tumu:

1056 case RISCVVector::BI__builtin_rvv_vssra_vx_tumu:

1057 case RISCVVector::BI__builtin_rvv_vssrl_vv_tumu:

1058 case RISCVVector::BI__builtin_rvv_vssrl_vx_tumu:

1059 case RISCVVector::BI__builtin_rvv_vnclip_wv_tumu:

1060 case RISCVVector::BI__builtin_rvv_vnclip_wx_tumu:

1061 case RISCVVector::BI__builtin_rvv_vnclipu_wv_tumu:

1062 case RISCVVector::BI__builtin_rvv_vnclipu_wx_tumu:

1063 return SemaRef.BuiltinConstantArgRange(TheCall, 4, 0, 3);

1064 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm:

1065 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm:

1066 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm:

1067 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm:

1068 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm:

1069 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm:

1070 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm:

1071 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm:

1072 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm:

1073 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm:

1074 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm:

1075 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm:

1076 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm:

1077 case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm:

1078 return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 4);

1079 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm:

1080 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm:

1081 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm:

1082 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm:

1083 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm:

1084 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm:

1085 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm:

1086 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm:

1087 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm:

1088 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm:

1089 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm:

1090 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm:

1091 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm:

1092 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm:

1093 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm:

1094 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm:

1095 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm:

1096 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm:

1097 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm:

1098 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm:

1099 case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm:

1100 case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm:

1101 case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm:

1102 case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm:

1103 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tu:

1104 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tu:

1105 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tu:

1106 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_tu:

1107 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_tu:

1108 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_tu:

1109 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_tu:

1110 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_tu:

1111 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_tu:

1112 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_tu:

1113 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tu:

1114 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tu:

1115 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tu:

1116 case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_tu:

1117 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_m:

1118 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_m:

1119 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_m:

1120 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_m:

1121 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_m:

1122 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_m:

1123 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_m:

1124 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_m:

1125 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_m:

1126 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_m:

1127 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_m:

1128 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_m:

1129 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_m:

1130 case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_m:

1131 return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 4);

1132 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tu:

1133 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tu:

1134 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tu:

1135 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tu:

1136 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tu:

1137 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tu:

1138 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tu:

1139 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tu:

1140 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tu:

1141 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tu:

1142 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tu:

1143 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tu:

1144 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tu:

1145 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tu:

1146 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tu:

1147 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tu:

1148 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tu:

1149 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tu:

1150 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tu:

1151 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tu:

1152 case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_tu:

1153 case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tu:

1154 case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tu:

1155 case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_tu:

1156 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm:

1157 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm:

1158 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm:

1159 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm:

1160 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm:

1161 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm:

1162 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm:

1163 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm:

1164 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm:

1165 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm:

1166 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm:

1167 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm:

1168 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm:

1169 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm:

1170 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm:

1171 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm:

1172 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm:

1173 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm:

1174 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm:

1175 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm:

1176 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm:

1177 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm:

1178 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm:

1179 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm:

1180 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm:

1181 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm:

1182 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tu:

1183 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tu:

1184 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tu:

1185 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tu:

1186 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tu:

1187 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tu:

1188 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tu:

1189 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tu:

1190 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tu:

1191 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tu:

1192 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tu:

1193 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tu:

1194 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tu:

1195 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tu:

1196 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tu:

1197 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tu:

1198 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_tu:

1199 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_tu:

1200 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_tu:

1201 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_tu:

1202 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_tu:

1203 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tu:

1204 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tu:

1205 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tu:

1206 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_tu:

1207 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_tu:

1208 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_m:

1209 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_m:

1210 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_m:

1211 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_m:

1212 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_m:

1213 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_m:

1214 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_m:

1215 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_m:

1216 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_m:

1217 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_m:

1218 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_m:

1219 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_m:

1220 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_m:

1221 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_m:

1222 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_m:

1223 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_m:

1224 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_m:

1225 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_m:

1226 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_m:

1227 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_m:

1228 case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_m:

1229 case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_m:

1230 case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_m:

1231 case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_m:

1232 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tum:

1233 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tum:

1234 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tum:

1235 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_tum:

1236 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_tum:

1237 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_tum:

1238 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_tum:

1239 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_tum:

1240 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_tum:

1241 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_tum:

1242 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tum:

1243 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tum:

1244 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tum:

1245 case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_tum:

1246 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tumu:

1247 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tumu:

1248 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tumu:

1249 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_tumu:

1250 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_tumu:

1251 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_tumu:

1252 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_tumu:

1253 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_tumu:

1254 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_tumu:

1255 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_tumu:

1256 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tumu:

1257 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tumu:

1258 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tumu:

1259 case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_tumu:

1260 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_mu:

1261 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_mu:

1262 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_mu:

1263 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_mu:

1264 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_mu:

1265 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_mu:

1266 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_mu:

1267 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_mu:

1268 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_mu:

1269 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_mu:

1270 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_mu:

1271 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_mu:

1272 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_mu:

1273 case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_mu:

1274 return SemaRef.BuiltinConstantArgRange(TheCall, 3, 0, 4);

1275 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_m:

1276 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_m:

1277 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_m:

1278 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_m:

1279 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_m:

1280 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_m:

1281 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_m:

1282 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_m:

1283 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_m:

1284 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_m:

1285 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_m:

1286 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_m:

1287 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_m:

1288 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_m:

1289 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_m:

1290 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_m:

1291 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_m:

1292 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_m:

1293 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_m:

1294 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_m:

1295 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_m:

1296 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_m:

1297 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_m:

1298 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_m:

1299 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_m:

1300 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_m:

1301 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tum:

1302 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tum:

1303 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tum:

1304 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tum:

1305 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tum:

1306 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tum:

1307 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tum:

1308 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tum:

1309 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tum:

1310 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tum:

1311 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tum:

1312 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tum:

1313 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tum:

1314 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tum:

1315 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tum:

1316 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tum:

1317 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tum:

1318 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tum:

1319 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tum:

1320 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tum:

1321 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tum:

1322 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tum:

1323 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tum:

1324 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tum:

1325 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tum:

1326 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tum:

1327 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tum:

1328 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tum:

1329 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tum:

1330 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tum:

1331 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tum:

1332 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tum:

1333 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tum:

1334 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tum:

1335 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tum:

1336 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tum:

1337 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_tum:

1338 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_tum:

1339 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_tum:

1340 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_tum:

1341 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_tum:

1342 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tum:

1343 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tum:

1344 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tum:

1345 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_tum:

1346 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_tum:

1347 case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_tum:

1348 case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tum:

1349 case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tum:

1350 case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_tum:

1351 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tumu:

1352 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tumu:

1353 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tumu:

1354 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tumu:

1355 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tumu:

1356 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tumu:

1357 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tumu:

1358 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tumu:

1359 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tumu:

1360 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tumu:

1361 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tumu:

1362 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tumu:

1363 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tumu:

1364 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tumu:

1365 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tumu:

1366 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tumu:

1367 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tumu:

1368 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tumu:

1369 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tumu:

1370 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tumu:

1371 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tumu:

1372 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tumu:

1373 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tumu:

1374 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tumu:

1375 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tumu:

1376 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tumu:

1377 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tumu:

1378 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tumu:

1379 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tumu:

1380 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tumu:

1381 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tumu:

1382 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tumu:

1383 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tumu:

1384 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tumu:

1385 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tumu:

1386 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tumu:

1387 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_tumu:

1388 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_tumu:

1389 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_tumu:

1390 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_tumu:

1391 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_tumu:

1392 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tumu:

1393 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tumu:

1394 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tumu:

1395 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_tumu:

1396 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_tumu:

1397 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_mu:

1398 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_mu:

1399 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_mu:

1400 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_mu:

1401 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_mu:

1402 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_mu:

1403 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_mu:

1404 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_mu:

1405 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_mu:

1406 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_mu:

1407 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_mu:

1408 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_mu:

1409 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_mu:

1410 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_mu:

1411 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_mu:

1412 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_mu:

1413 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_mu:

1414 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_mu:

1415 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_mu:

1416 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_mu:

1417 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_mu:

1418 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_mu:

1419 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_mu:

1420 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_mu:

1421 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_mu:

1422 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_mu:

1423 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_mu:

1424 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_mu:

1425 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_mu:

1426 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_mu:

1427 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_mu:

1428 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_mu:

1429 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_mu:

1430 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_mu:

1431 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_mu:

1432 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_mu:

1433 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_mu:

1434 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_mu:

1435 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_mu:

1436 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_mu:

1437 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_mu:

1438 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_mu:

1439 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_mu:

1440 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_mu:

1441 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_mu:

1442 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_mu:

1443 return SemaRef.BuiltinConstantArgRange(TheCall, 4, 0, 4);

1444 case RISCV::BI__builtin_riscv_ntl_load:

1445 case RISCV::BI__builtin_riscv_ntl_store:

1448 assert((BuiltinID == RISCV::BI__builtin_riscv_ntl_store ||

1449 BuiltinID == RISCV::BI__builtin_riscv_ntl_load) &&

1450 "Unexpected RISC-V nontemporal load/store builtin!");

1451 bool IsStore = BuiltinID == RISCV::BI__builtin_riscv_ntl_store;

1452 unsigned NumArgs = IsStore ? 3 : 2;

1453

1454 if (SemaRef.checkArgCountAtLeast(TheCall, NumArgs - 1))

1455 return true;

1456

1457 if (SemaRef.checkArgCountAtMost(TheCall, NumArgs))

1458 return true;

1459

1460

1461

1462 if (TheCall->getNumArgs() == NumArgs &&

1463 SemaRef.BuiltinConstantArgRange(TheCall, NumArgs - 1, 2, 5))

1464 return true;

1465

1466 Expr *PointerArg = TheCall->getArg(0);

1468 SemaRef.DefaultFunctionArrayLvalueConversion(PointerArg);

1469

1470 if (PointerArgResult.isInvalid())

1471 return true;

1472 PointerArg = PointerArgResult.get();

1473

1475 if (!PtrType) {

1476 Diag(DRE->getBeginLoc(), diag::err_nontemporal_builtin_must_be_pointer)

1478 return true;

1479 }

1480

1487 diag::err_nontemporal_builtin_must_be_pointer_intfltptr_or_vector)

1489 return true;

1490 }

1491

1492 if (!IsStore) {

1493 TheCall->setType(ValType);

1494 return false;

1495 }

1496

1499 Context, ValType, false);

1500 ValArg =

1503 return true;

1504

1505 TheCall->setArg(1, ValArg.get());

1506 TheCall->setType(Context.VoidTy);

1507 return false;

1508 }

1509

1510 return false;

1511}

1514 const llvm::StringMap &FeatureMap) {

1518 unsigned MinElts = Info.EC.getKnownMinValue();

1519

1521 !FeatureMap.lookup("zve64d"))

1522 Diag(Loc, diag::err_riscv_type_requires_extension) << Ty << "zve64d";

1523

1524

1526 MinElts == 1) &&

1527 !FeatureMap.lookup("zve64x"))

1528 Diag(Loc, diag::err_riscv_type_requires_extension) << Ty << "zve64x";

1530 !FeatureMap.lookup("zvfhmin") &&

1531 !FeatureMap.lookup("xandesvpackfph"))

1533 Diag(Loc, diag::err_riscv_type_requires_extension)

1534 << Ty << "zvfh, zvfhmin or xandesvpackfph";

1535 } else {

1536 Diag(Loc, diag::err_riscv_type_requires_extension)

1537 << Ty << "zvfh or zvfhmin";

1538 }

1540 !FeatureMap.lookup("zvfbfmin") &&

1541 !FeatureMap.lookup("xandesvbfhcvt") &&

1542 !FeatureMap.lookup("experimental-zvfbfa"))

1544 Diag(Loc, diag::err_riscv_type_requires_extension)

1545 << Ty << "zvfbfmin or xandesvbfhcvt";

1546 } else {

1547 Diag(Loc, diag::err_riscv_type_requires_extension) << Ty << "zvfbfmin";

1548 }

1550 !FeatureMap.lookup("zve32f"))

1551 Diag(Loc, diag::err_riscv_type_requires_extension) << Ty << "zve32f";

1552

1553

1554 else if (!FeatureMap.lookup("zve32x"))

1555 Diag(Loc, diag::err_riscv_type_requires_extension) << Ty << "zve32x";

1556}

1566

1567 auto ValidScalableConversion = [](QualType FirstType, QualType SecondType) {

1569 return false;

1570

1571 const auto *VecTy = SecondType->getAs<VectorType>();

1573 };

1574

1575 return ValidScalableConversion(srcTy, destTy) ||

1576 ValidScalableConversion(destTy, srcTy);

1577}

1580

1581 if (const auto *A = D->getAttr()) {

1583 diag::warn_riscv_repeated_interrupt_attribute);

1584 Diag(A->getLocation(), diag::note_riscv_repeated_interrupt_attribute);

1585 return;

1586 }

1587

1588

1589

1590

1591

1592

1593

1594

1595

1596

1598 Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)

1600 return;

1601 }

1602

1604 Diag(D->getLocation(), diag::warn_interrupt_signal_attribute_invalid)

1605 << 2 << 0 << 0;

1606 return;

1607 }

1608

1610 Diag(D->getLocation(), diag::warn_interrupt_signal_attribute_invalid)

1611 << 2 << 0 << 1;

1612 return;

1613 }

1614

1616 return;

1617

1618 bool HasSiFiveCLICType = false;

1619 bool HasUnaryType = false;

1620

1621 SmallSet<RISCVInterruptAttr::InterruptType, 2> Types;

1622 for (unsigned ArgIndex = 0; ArgIndex < AL.getNumArgs(); ++ArgIndex) {

1623 RISCVInterruptAttr::InterruptType Type;

1624 StringRef TypeString;

1626

1627 if (.checkStringLiteralArgumentAttr(AL, ArgIndex, TypeString, &Loc))

1628 return;

1629

1630 if (!RISCVInterruptAttr::ConvertStrToInterruptType(TypeString, Type)) {

1631 std::string TypeLiteral = ("\"" + TypeString + "\"").str();

1632 Diag(AL.getLoc(), diag::warn_attribute_type_not_supported)

1633 << AL << TypeLiteral << Loc;

1634 return;

1635 }

1636

1637 switch (Type) {

1638 case RISCVInterruptAttr::machine:

1639

1640

1641 break;

1642 case RISCVInterruptAttr::SiFiveCLICPreemptible:

1643 case RISCVInterruptAttr::SiFiveCLICStackSwap:

1644

1645 HasSiFiveCLICType = true;

1646 break;

1647 case RISCVInterruptAttr::supervisor:

1648 case RISCVInterruptAttr::rnmi:

1649 case RISCVInterruptAttr::qcinest:

1650 case RISCVInterruptAttr::qcinonest:

1651

1652

1653 HasUnaryType = true;

1654 break;

1655 }

1656

1657 Types.insert(Type);

1658 }

1659

1660 if (HasUnaryType && Types.size() > 1) {

1661 Diag(AL.getLoc(), diag::err_riscv_attribute_interrupt_invalid_combination);

1662 return;

1663 }

1664

1665 if (HasUnaryType && HasSiFiveCLICType) {

1666 Diag(AL.getLoc(), diag::err_riscv_attribute_interrupt_invalid_combination);

1667 return;

1668 }

1669

1670

1672 Types.insert(RISCVInterruptAttr::machine);

1673

1675 llvm::StringMap FunctionFeatureMap;

1676 getASTContext().getFunctionFeatureMap(FunctionFeatureMap,

1677 dyn_cast(D));

1678

1679 auto HasFeature = [&](StringRef FeatureName) -> bool {

1680 return TI.hasFeature(FeatureName) || FunctionFeatureMap.lookup(FeatureName);

1681 };

1682

1683 for (RISCVInterruptAttr::InterruptType Type : Types) {

1684 switch (Type) {

1685

1686 case RISCVInterruptAttr::qcinest:

1687 case RISCVInterruptAttr::qcinonest: {

1688 if (("experimental-xqciint")) {

1690 diag::err_riscv_attribute_interrupt_requires_extension)

1691 << RISCVInterruptAttr::ConvertInterruptTypeToStr(Type) << "Xqciint";

1692 return;

1693 }

1694 } break;

1695

1696 case RISCVInterruptAttr::SiFiveCLICPreemptible:

1697 case RISCVInterruptAttr::SiFiveCLICStackSwap: {

1698 if (("experimental-xsfmclic")) {

1700 diag::err_riscv_attribute_interrupt_requires_extension)

1701 << RISCVInterruptAttr::ConvertInterruptTypeToStr(Type)

1702 << "XSfmclic";

1703 return;

1704 }

1705 } break;

1706 case RISCVInterruptAttr::rnmi: {

1709 diag::err_riscv_attribute_interrupt_requires_extension)

1710 << RISCVInterruptAttr::ConvertInterruptTypeToStr(Type) << "Smrnmi";

1711 return;

1712 }

1713 } break;

1714 default:

1715 break;

1716 }

1717 }

1718

1720 Types.end());

1721

1723 getASTContext(), AL, TypesVec.data(), TypesVec.size()));

1724}

1732 if (Ext.empty())

1733 return false;

1734

1735 if (!Ext.consume_front("+"))

1736 return false;

1737

1738 return -1 != RISCVISAInfo::getRISCVFeaturesBitsInfo(Ext).second;

1739}

1745

1747 Param.split(AttrStrs, ';');

1748

1749 bool HasArch = false;

1750 bool HasPriority = false;

1751 bool HasDefault = false;

1752 bool DuplicateAttr = false;

1753 for (StringRef AttrStr : AttrStrs) {

1754 AttrStr = AttrStr.trim();

1755

1756 if (AttrStr.starts_with("arch=+")) {

1757 DuplicateAttr = HasArch;

1758 HasArch = true;

1760 getASTContext().getTargetInfo().parseTargetAttr(AttrStr);

1761

1762 if (TargetAttr.Features.empty() ||

1763 llvm::any_of(TargetAttr.Features, [&](const StringRef Ext) {

1764 return !isValidFMVExtension(Ext);

1765 }))

1766 return Diag(Loc, diag::warn_unsupported_target_attribute)

1768 } else if (AttrStr == "default") {

1769 DuplicateAttr = HasDefault;

1770 HasDefault = true;

1771 } else if (AttrStr.consume_front("priority=")) {

1772 DuplicateAttr = HasPriority;

1773 HasPriority = true;

1774 unsigned Digit;

1775 if (AttrStr.getAsInteger(0, Digit))

1776 return Diag(Loc, diag::warn_unsupported_target_attribute)

1778 } else {

1779 return Diag(Loc, diag::warn_unsupported_target_attribute)

1781 }

1782 }

1783

1784 if (((HasPriority || HasArch) && HasDefault) || DuplicateAttr ||

1785 (HasPriority && !HasArch))

1786 return Diag(Loc, diag::warn_unsupported_target_attribute)

1788

1789 NewParam = Param;

1790 return false;

1791}

1797

1798 assert(Params.size() == Locs.size() &&

1799 "Mismatch between number of string parameters and locations");

1800

1801 bool HasDefault = false;

1802 for (unsigned I = 0, E = Params.size(); I < E; ++I) {

1803 const StringRef Param = Params[I].trim();

1805

1807 Param.split(AttrStrs, ';');

1808

1809 bool IsPriority = false;

1810 bool IsDefault = false;

1811 for (StringRef AttrStr : AttrStrs) {

1812 AttrStr = AttrStr.trim();

1813

1814 if (AttrStr.starts_with("arch=+")) {

1816 getASTContext().getTargetInfo().parseTargetAttr(AttrStr);

1817

1818 if (TargetAttr.Features.empty() ||

1819 llvm::any_of(TargetAttr.Features, [&](const StringRef Ext) {

1820 return !isValidFMVExtension(Ext);

1821 }))

1822 return Diag(Loc, diag::warn_unsupported_target_attribute)

1824 } else if (AttrStr == "default") {

1825 IsDefault = true;

1826 HasDefault = true;

1827 } else if (AttrStr.consume_front("priority=")) {

1828 IsPriority = true;

1829 unsigned Digit;

1830 if (AttrStr.getAsInteger(0, Digit))

1831 return Diag(Loc, diag::warn_unsupported_target_attribute)

1833 } else {

1834 return Diag(Loc, diag::warn_unsupported_target_attribute)

1836 }

1837 }

1838

1839 if (IsPriority && IsDefault)

1840 return Diag(Loc, diag::warn_unsupported_target_attribute)

1842

1843 if (llvm::is_contained(NewParams, Param))

1844 Diag(Loc, diag::warn_target_clone_duplicate_options);

1845 NewParams.push_back(Param);

1846 }

1847 if (!HasDefault)

1848 return Diag(Locs[0], diag::err_target_clone_must_have_default);

1849

1850 return false;

1851}