High Priority Interrupts - ESP32 (original) (raw)

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The Xtensa architecture supports 32 interrupts, divided over 7 priority levels from level 1 to 7, with level 7 being an non-maskable interrupt (NMI), plus an assortment of exceptions. On the ESP32, the Interrupt Allocation can route most interrupt sources to these interrupts via the interrupt mux. Normally, interrupts are written in C, but ESP-IDF allows high-priority interrupts to be written in assembly as well, resulting in very low interrupt latencies.

Interrupt Priorities

Priority Level Symbol Remark
1 N/A Exception and low priority interrupts, handled by ESP-IDF.
2-3 N/A Medium priority interrupts, handled by ESP-IDF.
4 xt_highint4 High priority interrupt, free to use. [1]
5 xt_highint5 Normally used by ESP-IDF debug logic. [1]
NMI xt_nmi Non-maskable interrupt, free to use.
dbg xt_debugexception Debug exception. Called on e.g., a BREAK instruction. [2]

Using these symbols is done by creating an assembly file with suffix .S and defining the named symbols, like this:

.section .iram1,"ax"
.global     xt_highint4
.type       xt_highint4,@function
.align      4

xt_highint5: ... your code here rsr a0, EXCSAVE_5 rfi 5

For a real-life example, see the esp_system/port/soc/esp32/highint_hdl.S file; the panic handler interrupt is implemented there.

Notes

When CONFIG_BTDM_CTRL_HLI is enabled, C code is also called from a high-priority interrupt, this is possible thanks to some additional protection added to it.

.global ld_include_my_isr_file ld_include_my_isr_file:

Here it is called ld_include_my_isr_file but can have any name, as long as it is not defined anywhere else in the project.

Then, in the component CMakeLists.txt, add this name as an unresolved symbol to the ld command line arguments:

target_link_libraries(${COMPONENT_TARGET} "-u ld_include_my_isr_file")

This will ensure the linker to always includes the file defining ld_include_my_isr_file, so that the ISR is always linked.

See system/nmi_isr for an example of how to implement a custom NMI handler on Xtensa-based targets.


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