Andi Kleen - Re: [patch] tuning gcc for AMDFAM10 processor (patch 1) (original) (raw)

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• From: Andi Kleen
• To: "Jagasia, Harsha"
• Cc: gcc-patches at gcc dot gnu dot org, "Meissner, Michael" , "rajagopal, dwarak"
• Date: Thu, 1 Feb 2007 06:19:45 +0100
• Subject: Re: [patch] tuning gcc for AMDFAM10 processor (patch 1)
• References: D5B24B5251882048AD03DDFA431BB79059CF2E@SAUSEXMB3.amd.com

On Wednesday 31 January 2007 23:06, Jagasia, Harsha wrote:

Also I was wondering how hard it would be to make gcc detect code patterns automatically for the new bitfield instructions?

We are looking to submit a patch before stage 2 closes that can use the new extractq/insertq instructions for zero_extract, but we are not sure how viable it will be because these are SSEx instructions. But, I am not sure if you were referring to that or to auto generating popcnt/lzcnt instructions, which happen to be integer instructions.

I guess they can be generated for __builtin_popcount/__builtin_ffs[1] Detecting straight C patterns for these would be likely fruitless because there is no standard idiom to write them.

[1] That doesn't seem to exist right now, but perhaps it should be added.

Can you give us some more details on what will be useful for you so we can target the appropriate instructions and come up with the right patterns?

I personally have no immediate use for it, i was just curious after reading the patches.

-Andi

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  • Re: [patch] tuning gcc for AMDFAM10 processor (patch 1)
    * From: Andrew Pinski