Richard Henderson - ia32 inter-unit move fixes, part 1 (original) (raw)

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Twice in the last two weeks, it has come to my attention that we're not doing the right thing with respect to allowing or disallowing inter-unit moves. That is, direct moves between the general and sse register sets.

In the case of Intel chips, we'd like to allow them, but not make it so easy that it becomes an easy register preference for the allocator.

In the case of AMD chips, we'd like to disallow them, as they prefer we bounce the data through memory.

At present, we're allowing inter-unit moves in some cases, and disallowing them in others, without regard to what cpu we're tuning for.

In this patch, I rename the existing Y constraint to Y2, so that I can add a Yi constraint for use when inter-unit moves are allowed. In the balance of the patch, I adjust the md files to match. No uses of Yi are yet included, only renaming from the old name. For the insn patterns that require SSE2 in the predicate, I rename to 'x', rather than use the conditional 'Y2', which should be reserved for when SSE2 might not be available.

Tested on x86_64-linux.

r~

    * config/i386/constraints.md (Y2): Rename from Y.
    (Yi): New constraint. 
    * config/i386/i386.md (movsi_1, movdi_2, pushdf_nointeger,
    pushdf_integer, movdf_nointeger, movdf_integer, zero_extendsidi2_32,
    zero_extendsidi2_rex64, truncxfdf2_mixed): Change Y constraints to Y2.
    (extendsfdf2_mixed, extendsfdf2_sse, truncdfsf_fast_mixed,
    truncdfsf_fast_sse, truncdfsf_mixed, fix_truncdfdi_sse,
    fix_truncdfsi_sse, floatsidf2_mixed, floatsidf2_sse,
    floatdidf2_mixed, floatdidf2_sse, absnegdf2_mixed,
    absnegdf2_sse, sse_setccdf, fop_df_comm_mixed, fop_df_comm_sse,
    fop_df_1_mixed, fop_df_1_sse): Change Y constraints to x.
    * config/i386/mmx.md (mov<MMXMODEI>_internal_rex64,
    mov<MMXMODEI>_internal, movv2sf_internal_rex64, movv2sf_internal,
    vec_extractv2si_1): Change Y constraints to Y2.
    * config/i386/sse.md (vec_setv4sf_0, vec_concatv2df, vec_dupv4si,
    vec_dupv2di, sse2_concatv2si, vec_concatv4si_1, vec_concatv2di):
    Change Y constraints to Y2.
    (sse2_loadld): Change Y constraints to x.

--- config/i386/constraints.md (revision 121660) +++ config/i386/constraints.md (local) @@ -83,8 +83,16 @@ (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS" "Any SSE register.")

-(define_register_constraint "Y" "TARGET_SSE2? SSE_REGS : NO_REGS"

;; Integer constant constraints. (define_constraint "I" --- config/i386/i386.md (revision 121660) +++ config/i386/i386.md (local) @@ -1187,9 +1187,9 @@

(define_insn "*movsi_1" [(set (match_operand:SI 0 "nonimmediate_operand" - "=r ,m ,*y,*y,?rm,?*y,*x,*x,?r,m ,?*Y,*x") + "=r ,m ,*y,*y,?rm,?*y,*x,*x,?r ,m ,?*Y2,*x") (match_operand:SI 1 "general_operand" - "rinm,rin,C ,*y,*y ,rm ,C ,*x,*Y,*x,r ,m "))] + "rinm,rin,C ,*y,*y ,rm ,C ,*x,*Y2,*x,r ,m "))] "!(MEM_P (operands[0]) && MEM_P (operands[1]))" { switch (get_attr_type (insn)) @@ -1981,9 +1981,9 @@

(define_insn "*movdi_2" [(set (match_operand:DI 0 "nonimmediate_operand" - "=r ,o ,y,my,*y,*Y,m ,*Y,*Y,*x,m ,*x,*x") + "=r ,o ,y,my,*y,*Y2,m ,*Y2,*Y2,*x,m ,*x,*x") (match_operand:DI 1 "general_operand" - "riFo,riF,C ,*y ,m ,C ,*Y,*Y,m ,C ,*x,*x,m "))] + "riFo,riF,C ,*y ,m ,C ,*Y2,*Y2,m ,C ,*x,*x,m "))] "!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ # @@ -2437,7 +2437,7 @@

(define_insn "*pushdf_nointeger" [(set (match_operand:DF 0 "push_operand" "=<,<,<,<") - (match_operand:DF 1 "general_no_elim_operand" "f,Fo,*r,Y"))] + (match_operand:DF 1 "general_no_elim_operand" "f,Fo,r,Y2"))] "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES" { / This insn should be already split before reg-stack. */ @@ -2449,7 +2449,7 @@

(define_insn "pushdf_integer" [(set (match_operand:DF 0 "push_operand" "=<,<,<") - (match_operand:DF 1 "general_no_elim_operand" "f,rFo,Y"))] + (match_operand:DF 1 "general_no_elim_operand" "f,rFo,Y2"))] "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES" { / This insn should be already split before reg-stack. */ @@ -2489,9 +2489,9 @@

(define_insn "movdf_nointeger" [(set (match_operand:DF 0 "nonimmediate_operand" - "=f,m,f,r ,o ,Yx,Yx,Yx ,m ") + "=f,m,f,r ,o ,Y2x,Y2x,Y2x ,m ") (match_operand:DF 1 "general_operand" - "fm,f,G,roF,Fr,C ,Yx,mYx,Yx"))] + "fm,f,G,roF,Fr,C ,Y2x,mY2x,Y2*x"))] "!(MEM_P (operands[0]) && MEM_P (operands[1])) && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT) && (reload_in_progress || reload_completed @@ -2611,9 +2611,9 @@

(define_insn "movdf_integer" [(set (match_operand:DF 0 "nonimmediate_operand" - "=f,m,f,r ,o ,Yx,Yx,Yx,m ") + "=f,m,f,r ,o ,Y2x,Y2x,Y2x,m ") (match_operand:DF 1 "general_operand" - "fm,f,G,roF,Fr,C ,Yx,m ,Yx"))] + "fm,f,G,roF,Fr,C ,Y2x,m ,Y2*x"))] "!(MEM_P (operands[0]) && MEM_P (operands[1])) && ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT) && (reload_in_progress || reload_completed @@ -3269,8 +3269,9 @@ ")

(define_insn "zero_extendsidi2_32"

(define_insn "*extendsfdf2_mixed"

(define_insn "*truncdfsf_fast_mixed"

(define_insn "*truncdfsf_mixed"

(define_insn "fix_truncdfdi_sse" [(set (match_operand:DI 0 "register_operand" "=r,r") - (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))] + (fix:DI (match_operand:DF 1 "nonimmediate_operand" "x,xm")))] "TARGET_64BIT && TARGET_SSE2 && (!TARGET_FISTTP || TARGET_SSE_MATH)" "cvttsd2si{q}\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") @@ -4225,7 +4228,7 @@

(define_insn "fix_truncdfsi_sse" [(set (match_operand:SI 0 "register_operand" "=r,r") - (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))] + (fix:SI (match_operand:DF 1 "nonimmediate_operand" "x,xm")))] "TARGET_SSE2 && (!TARGET_FISTTP || TARGET_SSE_MATH)" "cvttsd2si\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") @@ -4668,7 +4671,7 @@ "")

(define_insn "*floatsidf2_mixed"

(define_insn "*floatsidf2_sse"

(define_insn "*floatdidf2_mixed"

(define_insn "*floatdidf2_sse"

(define_insn "*absnegdf2_mixed"

(define_insn "*absnegdf2_sse"

(define_insn "*sse_setccdf"

@@ -2445,10 +2445,10 @@ (set_attr "mode" "DF")])

(define_insn "*vec_concatv2df"

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