Paolo Bonzini - [dataflow] fix reversed logic in combine (original) (raw)

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• From: Paolo Bonzini
• To: GCC Patches , Kenneth Zadeck
• Date: Wed, 21 Feb 2007 17:27:19 +0100
• Subject: [dataflow] fix reversed logic in combine

combine is not really a local pass, it does some analysis on registers where the sole definition dominates all uses. On trunk, it does so by looking at global_live_at_start having a pseudo for the entry basic block. On dataflow-branch, it looks at the pseudo *not being in the DF_UR* problem.The logic in trunk's combine with respect to uninitialized variables is
correct. We have to look at DF_LR_IN for the entry basic block to find variables that are not used uninitialized, and that fixes the bug.In fact, the name of UR is misleading, as it is a forward problem that computes *initialized* registers.Ok?Paolo

Index: combine.c

--- combine.c (revision 122195) +++ combine.c (working copy) @@ -1351,8 +1351,8 @@ set_nonzero_bits_and_sign_copies (rtx x, && REGNO (x) >= FIRST_PSEUDO_REGISTER /* If this register is undefined at the start of the file, we can't say what its contents were. */

•  && REGNO_REG_SET_P

•     (DF_UR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))

•  && ! REGNO_REG_SET_P

•       (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
   && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)

  { if (set == 0 || GET_CODE (set) == CLOBBER)

@@ -8648,8 +8648,8 @@ reg_nonzero_bits_for_combine (rtx x, enu && DF_INSN_LUID (reg_stat[REGNO (x)].last_set) < subst_low_luid) || (REGNO (x) >= FIRST_PSEUDO_REGISTER && REG_N_SETS (REGNO (x)) == 1 - && REGNO_REG_SET_P - (DF_UR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))))) + && !REGNO_REG_SET_P + (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))))) { *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits; return NULL; @@ -8717,8 +8717,8 @@ reg_num_sign_bit_copies_for_combine (rtx && DF_INSN_LUID (reg_stat[REGNO (x)].last_set) < subst_low_luid) || (REGNO (x) >= FIRST_PSEUDO_REGISTER && REG_N_SETS (REGNO (x)) == 1 - && REGNO_REG_SET_P - (DF_UR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))))) + && !REGNO_REG_SET_P + (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))))) { *result = reg_stat[REGNO (x)].last_set_sign_bit_copies; return NULL; @@ -11613,8 +11613,8 @@ get_last_value_validate (rtx *loc, rtx i live at the beginning of the function, it is always valid. */ || (! (regno >= FIRST_PSEUDO_REGISTER && REG_N_SETS (regno) == 1 - && (REGNO_REG_SET_P - (DF_UR_IN (ENTRY_BLOCK_PTR->next_bb), regno))) + && !REGNO_REG_SET_P + (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)) && reg_stat[j].last_set_label > tick)) { if (replace) @@ -11723,8 +11723,8 @@ get_last_value (rtx x) || (reg_stat[regno].last_set_label < label_tick_ebb_start && (regno < FIRST_PSEUDO_REGISTER || REG_N_SETS (regno) != 1 - || ! (REGNO_REG_SET_P - (DF_UR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))) + || REGNO_REG_SET_P + (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))) return 0;

/* If the value was set in a later insn than the ones we are processing,

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  • Re: [dataflow] fix reversed logic in combine
    * From: Kenneth Zadeck