Bernd Schmidt - Blackfin patch: Generate valid shifts (original) (raw)

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• From: Bernd Schmidt <bernds_cb1 at t-online dot de>
• To: GCC Patches
• Date: Tue, 27 Feb 2007 14:57:00 +0100
• Subject: Blackfin patch: Generate valid shifts

Some of the shift instructions in the Blackfin backend weren't generating valid assembly - should output a half register instead of a full one. Fixed with this, committed as 122374.

Bernd

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Index: ChangeLog

--- ChangeLog (revision 122373) +++ ChangeLog (working copy) @@ -40,6 +40,9 @@ usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul, usmulhisi_hh_huh): New patterns. + * config/bfin/bfin.md (ssashiftv2hi3, ssashifthi3, lshiftv2hi3, + lshifthi3): Fix output template to use half reg for operand 2. + 2007-02-27 Andreas Schwab schwab@suse.de * Makefile.in (TEXI_GCCINSTALL_FILES): Add gcc-common.texi. Index: config/bfin/bfin.md

--- config/bfin/bfin.md (revision 122373) +++ config/bfin/bfin.md (working copy) @@ -3777,7 +3777,7 @@ (define_insn "ssashiftv2hi3" (ss_ashift:V2HI (match_dup 1) (match_dup 2))))] "" "@

• %0 = ASHIFT %1 BY %2 (V, S)%!

• %0 = ASHIFT %1 BY %h2 (V, S)%! %0 = %1 << %2 (V,S)%! %0 = %1 >>> %N2 (V,S)%!" [(set_attr "type" "dsp32")]) @@ -3791,7 +3791,7 @@ (define_insn "ssashifthi3" (ss_ashift:HI (match_dup 1) (match_dup 2))))] "" "@

• %0 = ASHIFT %1 BY %2 (V, S)%!

• %0 = ASHIFT %1 BY %h2 (V, S)%! %0 = %1 << %2 (V,S)%! %0 = %1 >>> %N2 (V,S)%!" [(set_attr "type" "dsp32")]) @@ -3805,7 +3805,7 @@ (define_insn "lshiftv2hi3" (ashift:V2HI (match_dup 1) (match_dup 2))))] "" "@

• %0 = LSHIFT %1 BY %2 (V)%!

• %0 = LSHIFT %1 BY %h2 (V)%! %0 = %1 << %2 (V)%! %0 = %1 >> %N2 (V)%!" [(set_attr "type" "dsp32")]) @@ -3819,7 +3819,7 @@ (define_insn "lshifthi3" (ashift:HI (match_dup 1) (match_dup 2))))] "" "@

• %0 = LSHIFT %1 BY %2 (V)%!

• %0 = LSHIFT %1 BY %h2 (V)%! %0 = %1 << %2 (V)%! %0 = %1 >> %N2 (V)%!" [(set_attr "type" "dsp32")])