Basic PowerPC Built-in Functions Available on all Configurations (Using the GNU Compiler Collection (GCC)) (original) (raw)

This function returns a value of 1 if the run-time CPU supports the HWCAP feature feature and returns 0 otherwise.

The __builtin_cpu_supports function requires GLIBC 2.23 or newer which exports the hardware capability bits. GCC defines the macro __BUILTIN_CPU_SUPPORTS__ if the__builtin_cpu_supports built-in function is fully supported.

If GCC was configured to use a GLIBC before 2.23, the built-in function __builtin_cpu_suports always returns a 0 and the compiler issues a warning.

‘4xxmac’

4xx CPU has a Multiply Accumulator.

‘altivec’

CPU has a SIMD/Vector Unit.

‘arch_2_05’

CPU supports ISA 2.05 (eg, POWER6)

‘arch_2_06’

CPU supports ISA 2.06 (eg, POWER7)

‘arch_2_07’

CPU supports ISA 2.07 (eg, POWER8)

‘arch_3_00’

CPU supports ISA 3.0 (eg, POWER9)

‘arch_3_1’

CPU supports ISA 3.1 (eg, POWER10)

‘archpmu’

CPU supports the set of compatible performance monitoring events.

‘booke’

CPU supports the Embedded ISA category.

‘cellbe’

CPU has a CELL broadband engine.

‘darn’

CPU supports the darn (deliver a random number) instruction.

‘dfp’

CPU has a decimal floating point unit.

‘dscr’

CPU supports the data stream control register.

‘ebb’

CPU supports event base branching.

‘efpdouble’

CPU has a SPE double precision floating point unit.

‘efpsingle’

CPU has a SPE single precision floating point unit.

‘fpu’

CPU has a floating point unit.

‘htm’

CPU has hardware transaction memory instructions.

‘htm-nosc’

Kernel aborts hardware transactions when a syscall is made.

‘htm-no-suspend’

CPU supports hardware transaction memory but does not support thetsuspend. instruction.

‘ic_snoop’

CPU supports icache snooping capabilities.

‘ieee128’

CPU supports 128-bit IEEE binary floating point instructions.

‘isel’

CPU supports the integer select instruction.

‘mma’

CPU supports the matrix-multiply assist instructions.

‘mmu’

CPU has a memory management unit.

‘notb’

CPU does not have a timebase (eg, 601 and 403gx).

‘pa6t’

CPU supports the PA Semi 6T CORE ISA.

‘power4’

CPU supports ISA 2.00 (eg, POWER4)

‘power5’

CPU supports ISA 2.02 (eg, POWER5)

‘power5+’

CPU supports ISA 2.03 (eg, POWER5+)

‘power6x’

CPU supports ISA 2.05 (eg, POWER6) extended opcodes mffgpr and mftgpr.

‘ppc32’

CPU supports 32-bit mode execution.

‘ppc601’

CPU supports the old POWER ISA (eg, 601)

‘ppc64’

CPU supports 64-bit mode execution.

‘ppcle’

CPU supports a little-endian mode that uses address swizzling.

‘scv’

Kernel supports system call vectored.

‘smt’

CPU support simultaneous multi-threading.

‘spe’

CPU has a signal processing extension unit.

‘tar’

CPU supports the target address register.

‘true_le’

CPU supports true little-endian mode.

‘ucache’

CPU has unified I/D cache.

‘vcrypto’

CPU supports the vector cryptography instructions.

‘vsx’

CPU supports the vector-scalar extension.

#ifdef BUILTIN_CPU_SUPPORTS if (__builtin_cpu_supports ("fpu")) { asm("fadd %0,%1,%2" : "=d"(dst) : "d"(src1), "d"(src2)); } else #endif { dst = __fadd (src1, src2); // Software FP addition function. }