PowerPC Function Attributes (Using the GNU Compiler Collection (GCC)) (original) (raw)
6.35.24 PowerPC Function Attributes ¶
These function attributes are supported by the PowerPC back end:
longcall ¶
shortcall
The longcall attribute indicates that the function might be far away from the call site and require a different (more expensive) calling sequence. Theshortcall attribute indicates that the function is always close enough for the shorter calling sequence to be used. These attributes override both the -mlongcall switch and the #pragma longcall setting.
See IBM RS/6000 and PowerPC Options, for more information on whether long calls are necessary.
target (options) ¶
As discussed in Common Function Attributes, this attribute allows specification of target-specific compilation options.
On the PowerPC, the following options are allowed:
‘altivec’ ¶
‘no-altivec’
Generate code that uses (does not use) AltiVec instructions. In 32-bit code, you cannot enable AltiVec instructions unless-mabi=altivec is used on the command line.
‘cmpb’ ¶
‘no-cmpb’
Generate code that uses (does not use) the compare bytes instruction implemented on the POWER6 processor and other processors that support the PowerPC V2.05 architecture.
‘dlmzb’ ¶
‘no-dlmzb’
Generate code that uses (does not use) the string-search ‘dlmzb’ instruction on the IBM 405, 440, 464 and 476 processors. This instruction is generated by default when targeting those processors.
‘fprnd’ ¶
‘no-fprnd’
Generate code that uses (does not use) the FP round to integer instructions implemented on the POWER5+ processor and other processors that support the PowerPC V2.03 architecture.
‘hard-dfp’ ¶
‘no-hard-dfp’
Generate code that uses (does not use) the decimal floating-point instructions implemented on some POWER processors.
‘isel’ ¶
‘no-isel’
Generate code that uses (does not use) ISEL instruction.
‘mfcrf’ ¶
‘no-mfcrf’
Generate code that uses (does not use) the move from condition register field instruction implemented on the POWER4 processor and other processors that support the PowerPC V2.01 architecture.
‘mulhw’ ¶
‘no-mulhw’
Generate code that uses (does not use) the half-word multiply and multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors. These instructions are generated by default when targeting those processors.
‘multiple’ ¶
‘no-multiple’
Generate code that uses (does not use) the load multiple word instructions and the store multiple word instructions.
‘update’ ¶
‘no-update’
Generate code that uses (does not use) the load or store instructions that update the base register to the address of the calculated memory location.
‘popcntb’ ¶
‘no-popcntb’
Generate code that uses (does not use) the popcount and double-precision FP reciprocal estimate instruction implemented on the POWER5 processor and other processors that support the PowerPC V2.02 architecture.
‘popcntd’ ¶
‘no-popcntd’
Generate code that uses (does not use) the popcount instruction implemented on the POWER7 processor and other processors that support the PowerPC V2.06 architecture.
‘powerpc-gfxopt’ ¶
‘no-powerpc-gfxopt’
Generate code that uses (does not use) the optional PowerPC architecture instructions in the Graphics group, including floating-point select.
‘powerpc-gpopt’ ¶
‘no-powerpc-gpopt’
Generate code that uses (does not use) the optional PowerPC architecture instructions in the General Purpose group, including floating-point square root.
‘recip-precision’ ¶
‘no-recip-precision’
Assume (do not assume) that the reciprocal estimate instructions provide higher-precision estimates than is mandated by the PowerPC ABI.
‘string’ ¶
‘no-string’
Generate code that uses (does not use) the load string instructions and the store string word instructions to save multiple registers and do small block moves.
‘vsx’ ¶
‘no-vsx’
Generate code that uses (does not use) vector/scalar (VSX) instructions, and also enable the use of built-in functions that allow more direct access to the VSX instruction set. In 32-bit code, you cannot enable VSX or AltiVec instructions unless-mabi=altivec is used on the command line.
‘friz’ ¶
‘no-friz’
Generate (do not generate) the friz instruction when the-funsafe-math-optimizations option is used to optimize rounding a floating-point value to 64-bit integer and back to floating point. The friz instruction does not return the same value if the floating-point number is too large to fit in an integer.
‘avoid-indexed-addresses’ ¶
‘no-avoid-indexed-addresses’
Generate code that tries to avoid (not avoid) the use of indexed load or store instructions.
‘paired’ ¶
‘no-paired’
Generate code that uses (does not use) the generation of PAIRED simd instructions.
‘longcall’ ¶
‘no-longcall’
Generate code that assumes (does not assume) that all calls are far away so that a longer more expensive calling sequence is required.
‘cpu=CPU’ ¶
Specify the architecture to generate code for when compiling the function. If you select the target("cpu=power7") attribute when generating 32-bit code, VSX and AltiVec instructions are not generated unless you use the -mabi=altivec option on the command line.
‘tune=TUNE’ ¶
Specify the architecture to tune for when compiling the function. If you do not specify the target("tune=TUNE") attribute and you do specify the target("cpu=CPU") attribute, compilation tunes for the CPU architecture, and not the default tuning specified on the command line.
On the PowerPC, the inliner does not inline a function that has different target options than the caller, unless the callee has a subset of the target options of the caller.