dlhdl.ProcessorConfig - Configure custom deep learning processor - MATLAB (original) (raw)
Namespace: dlhdl
Configure custom deep learning processor
Since R2020b
Description
Use the dlhdl.ProcessorConfig class to configure a custom processor, which is then passed on to the dlhdl.buildProcessor class to generate a custom deep learning processor.
Creation
The dlhdl.ProcessorConfig class creates a custom processor configuration object that you can use to specify the processor parameters. The processor parameters are then used by the dlhdl.buildProcessor class to build and generate code for your custom deep learning processor.
dlhdl.ProcessorConfig(Name,Value) creates a custom processor configuration object, with additional options specified by one or more name-value arguments.
Properties
System Level Properties
Reference design name, specified as a character vector
Example: 'AXI-Stream DDR memory Access : 3-AXIM'
Synthesis tool name, specified as a character vector.
Example: Xilinx Vivado
Specify the target device chip family name as a character vector
Example: 'Zynq'
Synthesis tool device name specified as a character vector. When you specify theTargetPlatform, this field is populated with the default value for that target platform.
Synthesis tool package name specified as a character vector. When you specify theTargetPlatform, this field is populated with the default value for that target platform.
Synthesis tool speed value specified as a character vector. When you specify theTargetPlatform, this field is populated with the default value for that target platform.
Example: -2
Specify the target board frequency in MHz.
Example: 220
Specify the name of the target board as a character vector.
Example: 'Xilinx Zynq ZC706 evaluation kit'
Specify the name of the bitstream whose processor configuration must be retrieved as a character vector.
Example: 'Bitstream','zcu102_single'
Top Level Properties
Specify whether the runtime input signals to the deep learning processor IP core are implemented as registers or ports.
Example: 'register
Specify whether the runtime output signals from the deep learning processor IP core are implemented as registers or ports.
Example: 'register'
Specify the deep learning processor IP core input interface option as a character vector
Example: 'register'
Specify the deep learning processor IP core output interface option as a character vector
Example: 'port'
Specify the deep learning processor IP core user interface option as a character vector
Example: 'port'
Specify the deep learning processor IP core module data type as a character vector.
Example: 'single'
Option to use vendor-specific floating point libraries, specified as a character vector. When the option is set to 'on' Deep Learning HDL Toolbox™ uses a mixture of native floating-point (NFP) and vendor-specific floating point IPs to generate HDL code. When the option is set to 'off' Deep Learning HDL Toolbox uses native floating-point (NFP) libraries to generate HDL code.
When you set ProcessorDataType to int8, you must set UseVendorLibrary to 'off'. The option is set to on when ProcessorDataType issingle.
Example: UseVendorLibrary = 'on'
Option to enable or disable layer normalization layer generation, specified as a string or character vector. When you enable this layer, Deep Learning HDL Toolbox enables generation of the fc andcustom processing modules.
Example: LayerNormalizationBlock = "on"
Processing Module conv Properties
Use this parameter to control generation of the convolution module as a part of the deep learning processor configuration.
Use this parameter to control generation of the LRN block as a part of the convolution module of the deep learning processor configuration.
Use this parameter to control generation of the segmentation block as a part of the convolution module of the deep learning processor configuration.
Option to enable or disable Gaussian error linear unit (GELU) block, specified as a character vector.
This parameter is the number of parallel 3-by-3 convolution kernel threads that are a part of the conv module within thedlhdl.ProcessorConfig object. To set theConvThreadNumber to 256 theProcessorDataType parameter must be set toint8 data type.
This parameter is a 3D matrix representing size of the input buffer RAM on the FPGA for the conv module.
This parameter is a 3D matrix representing output image size limited by theconv module BRAM size within thedlhdl.ProcessorConfig object.
This parameter is a positive integer representing the maximum input and output feature size as a part of the conv module within thedlhdl.ProcessorConfig object.
Processing Module fc Properties
Use this parameter to control generation of the fully connected module as a part of the deep learning processor configuration.
Use this parameter to control generation of the Softmax block as a part of the fully connected module of the deep learning processor configuration. When you set this property to off, the Softmax layer is still implemented in software.
Option to enable or disable Gaussian error linear unit (GELU) block, specified as a character vector.
This parameter is the number of parallel fc MAC threads that are a part of thefc module within the dlhdl.ProcessorConfig object. To set the FCThreadNumber to 32 or 64 theProcessorDataType parameter must be set toint8 data type.
This parameter is a 3D matrix representing size of the input buffer RAM on the FPGA for the fc module.
This parameter is an unsigned integer representing cache BRAM size limited by thefc module BRAM size within thedlhdl.ProcessorConfig object.
Processing Module custom Properties
Use this parameter to control generation of the adder module as a part of the deep learning processor configuration.
Use this parameter to control generation of the addition layer as a part of the custom module of the deep learning processor configuration.
Use this parameter to control generation of the mish layer as a part of the custom module of the deep learning processor configuration.
Use this parameter to control generation of the multiplication layer as a part of the custom module of the deep learning processor configuration.
Use this parameter to control generation of the resize2d layer as a part of the custom module of the deep learning processor configuration.
Use this parameter to control generation of the sigmoid layer as a part of the custom module of the deep learning processor configuration.
Use this parameter to control generation of the swish layer as a part of the custom module of the deep learning processor configuration.
Use this parameter to control generation of the tanh layer as a part of the custom module of the deep learning processor configuration.
This parameter is an unsigned integer representing cache BRAM size limited by theadder module BRAM size within thedlhdl.ProcessorConfig object.
This parameter is an unsigned integer representing cache BRAM size limited by theadder module BRAM size within thedlhdl.ProcessorConfig object.
Methods
| buildCalibrationBitstream | Generate calibration bitstream to obtain double data rate (DDR) RAM response time |
|---|---|
| deployCalibrationBitstream | Deploy calibration bitstream and generate calibration data file |
| getModuleProperty | Use the getModuleProperty method to get values of module properties within the dlhdl.ProcessorConfig object |
| setModuleProperty | Use the setModuleProperty method to set properties of modules within the dlhdl.ProcessorConfig object |
| estimatePerformance | Retrieve layer-level latencies and performance by usingestimatePerformance method |
| estimateResources | Return estimated resources used by custom bitstream configuration |
| optimizeConfigurationForNetwork | Update network-specific deep learning processor configuration with optimized deep learning processor configuration |
| openCustomLayerModel | Open a generated custom layer verification model to verify your custom layers |
| registerCustomLayer | Register the custom layer definition and Simulink model representation of the custom layer |
| verifyCustomLayerModel | Verify the functionality and accuracy of the custom layer by using the generated custom layer verification model |
Examples
Create a ProcessorConfig Object
Create a custom processor configuration. Save the ProcessorConfig object to hPC.
hPC = dlhdl.ProcessorConfig
The result is:
hPC =
Processing Module "conv"
ModuleGeneration: 'on'
LRNBlockGeneration: 'off'
SegmentationBlockGeneration: 'on'
GELUBlockGeneration: 'off'
ConvThreadNumber: 16
InputMemorySize: [227 227 3]
OutputMemorySize: [227 227 3]
FeatureSizeLimit: 2048
Processing Module "fc"
ModuleGeneration: 'on'
SoftmaxBlockGeneration: 'off'
GELUBlockGeneration: 'off'
FCThreadNumber: 4
InputMemorySize: 25088
OutputMemorySize: 4096
Processing Module "custom"
ModuleGeneration: 'on'
Addition: 'on'
MishLayer: 'off'
Multiplication: 'on'
Resize2D: 'off'
Sigmoid: 'off'
SwishLayer: 'off'
TanhLayer: 'off'
InputMemorySize: 40
OutputMemorySize: 120
Processor Top Level Properties
RunTimeControl: 'register'
RunTimeStatus: 'register'
InputStreamControl: 'register'
OutputStreamControl: 'register'
SetupControl: 'register'
ProcessorDataType: 'single'
UseVendorLibrary: 'on'
LayerNormalizationBlock: 'off'
System Level Properties
TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
TargetFrequency: 200
SynthesisTool: 'Xilinx Vivado'
ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
SynthesisToolChipFamily: 'Zynq UltraScale+'
SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
SynthesisToolPackageName: ''
SynthesisToolSpeedValue: ''Modify Properties of ProcessorConfig Object
Modify the TargetPlatform, SynthesisTool, andTargetFrequency properties of hPC.
hPC.TargetPlatform = 'Xilinx Zynq ZC706 evaluation kit';
hPC.SynthesisTool = 'Xilinx Vivado'; hPC.TargetFrequency = 180; hPC
The result is:
hPC =
Processing Module "conv"
ModuleGeneration: 'on'
LRNBlockGeneration: 'off'
SegmentationBlockGeneration: 'on'
GELUBlockGeneration: 'off'
ConvThreadNumber: 16
InputMemorySize: [227 227 3]
OutputMemorySize: [227 227 3]
FeatureSizeLimit: 2048
Processing Module "fc"
ModuleGeneration: 'on'
SoftmaxBlockGeneration: 'off'
GELUBlockGeneration: 'off'
FCThreadNumber: 4
InputMemorySize: 25088
OutputMemorySize: 4096
Processing Module "custom"
ModuleGeneration: 'on'
Addition: 'on'
MishLayer: 'off'
Multiplication: 'on'
Resize2D: 'off'
Sigmoid: 'off'
SwishLayer: 'off'
TanhLayer: 'off'
InputMemorySize: 40
OutputMemorySize: 120
Processor Top Level Properties
RunTimeControl: 'register'
RunTimeStatus: 'register'
InputStreamControl: 'register'
OutputStreamControl: 'register'
SetupControl: 'register'
ProcessorDataType: 'single'
UseVendorLibrary: 'on'
LayerNormalizationBlock: 'off'
System Level Properties
TargetPlatform: 'Xilinx Zynq ZC706 evaluation kit'
TargetFrequency: 180
SynthesisTool: 'Xilinx Vivado'
ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
SynthesisToolChipFamily: 'Zynq'
SynthesisToolDeviceName: 'xc7z045'
SynthesisToolPackageName: 'ffg900'
SynthesisToolSpeedValue: '-2'Retrieve ProcessorConfig Object for zcu102_single Bitstream
Retrieve the ProcessorConfig object for thezcu102_single bitstream and store the object inhPC.
hPC = dlhdl.ProcessorConfig('Bitstream','zcu102_single')
The result is:
hPC =
Processing Module "conv"
ModuleGeneration: 'on'
LRNBlockGeneration: 'off'
SegmentationBlockGeneration: 'on'
GELUBlockGeneration: 'off'
ConvThreadNumber: 16
InputMemorySize: [227 227 3]
OutputMemorySize: [227 227 3]
FeatureSizeLimit: 2048
Processing Module "fc"
ModuleGeneration: 'on'
SoftmaxBlockGeneration: 'off'
GELUBlockGeneration: 'off'
FCThreadNumber: 4
InputMemorySize: 25088
OutputMemorySize: 4096
Processing Module "custom"
ModuleGeneration: 'on'
Addition: 'on'
MishLayer: 'off'
Multiplication: 'on'
Resize2D: 'on'
Sigmoid: 'off'
SwishLayer: 'off'
TanhLayer: 'off'
InputMemorySize: 40
OutputMemorySize: 120
Processor Top Level Properties
RunTimeControl: 'register'
RunTimeStatus: 'register'
InputStreamControl: 'register'
OutputStreamControl: 'register'
SetupControl: 'register'
ProcessorDataType: 'single'
UseVendorLibrary: 'on'
LayerNormalizationBlock: 'off'
System Level Properties
TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
TargetFrequency: 220
SynthesisTool: 'Xilinx Vivado'
ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
SynthesisToolChipFamily: 'Zynq UltraScale+'
SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
SynthesisToolPackageName: ''
SynthesisToolSpeedValue: ''Set the ProcessorConfig Object Module Data Type to int8
Create a custom processor configuration. Save the ProcessorConfig object to hPC.
hPC = dlhdl.ProcessorConfig
Modify the ProcessorDataType to int8. When you setProcessorDataType to int8, you must setUseVendorLibrary to 'off'.
hPC.ProcessorDataType = 'int8' hPC.UseVendorLibrary = 'off'
The result is:
hPC =
Processing Module "conv"
ModuleGeneration: 'on'
LRNBlockGeneration: 'off'
SegmentationBlockGeneration: 'on'
GELUBlockGeneration: 'off'
ConvThreadNumber: 16
InputMemorySize: [227 227 3]
OutputMemorySize: [227 227 3]
FeatureSizeLimit: 2048
Processing Module "fc"
ModuleGeneration: 'on'
SoftmaxBlockGeneration: 'off'
GELUBlockGeneration: 'off'
FCThreadNumber: 4
InputMemorySize: 25088
OutputMemorySize: 4096
Processing Module "custom"
ModuleGeneration: 'on'
Addition: 'on'
MishLayer: 'off'
Multiplication: 'on'
Resize2D: 'off'
Sigmoid: 'off'
SwishLayer: 'off'
TanhLayer: 'off'
InputMemorySize: 40
OutputMemorySize: 120
Processor Top Level Properties
RunTimeControl: 'register'
RunTimeStatus: 'register'
InputStreamControl: 'register'
OutputStreamControl: 'register'
SetupControl: 'register'
ProcessorDataType: 'int8'
UseVendorLibrary: 'off'
LayerNormalizationBlock: 'off'
System Level Properties
TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
TargetFrequency: 200
SynthesisTool: 'Xilinx Vivado'
ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
SynthesisToolChipFamily: 'Zynq UltraScale+'
SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
SynthesisToolPackageName: ''
SynthesisToolSpeedValue: ''Version History
Introduced in R2020b