hdlcoder.Board.addExternalIOInterface - Define external IO interface for board object - MATLAB (original) (raw)

Class: hdlcoder.Board
Namespace: hdlcoder

Define external IO interface for board object

Syntax

addExternalIOInterface('InterfaceID',interfacename,'InterfaceType',interfacetype,'PortName',portname,'PortWidth',portwidth,'FPGAPin',pins,'IOPadConstraint',constraints)

Description

addExternalIOInterface('InterfaceID',[interfacename](#buqpiaj-1-interfacename),'InterfaceType',[interfacetype](#buqpiaj-1-interfacetype),'PortName',[portname](#buqpiaj-1-portname),'PortWidth',[portwidth](#buqpiaj-1-portwidth),'FPGAPin',[pins](#buqpiaj-1-pins),'IOPadConstraint',[constraints](#buqpiaj-1-constraints)) adds an external IO interface to an hdlcoder.Board object. You can add multiple external IO interfaces to your board object.

Use this method if your board has more than one external interface, or if you want to be able to predefine FPGA pin names for mapping from the HDL Workflow Advisor.

Input Arguments

expand all

Interface name, specified as a character vector. In the HDL Workflow Advisor, this name appears in the Target Platform Interfaces dropdown list.

Example: 'LEDs General Purpose'

Interface direction, specified as a character vector. In the HDL Workflow Advisor, when you specify a target interface for each of your DUT ports, this external IO interface is available only for ports with a matching direction.

For example, if you set interfacetype to 'OUT', this external IO interface is available only for Outport DUT ports.

Example: 'OUT'

Board top-level port name, specified as a character vector.

Example: 'GPLEDs'

Port bit width, specified as a positive integer. You can use DUT ports that have flattened word lengths greater than 128 bits. To model DUT ports that have word lengths greater than 128 bits, use vector data types. For example, to model a 512-bit Data port, use a vector port with four 128-bit scalar ports.

Example: 4

FPGA pin names, specified as a cell array of character vectors. The pin are ordered from the lowest bit to the highest bit. For example, if you list the pins as{'H18','AA14','AA13','AB15'}, and map them to a 4-bit port interface as [0:3], then:

• Bit 0 is mapped to H18
• Bit 1 is mapped to AA14
• Bit 2 is mapped to AA13
• Bit 3 is mapped to AB15

Example: {'H18','AA14','AA13','AB15'}

IO pad constraints, specified as a cell array of character vectors.

Example: {'IOSTANDARD = LVCMOS25'}

Example: {'IOSTANDARD = LVCMOS25','SLEW = SLOW'}

Tips

• For details about the external IO interface ports, pins, and constraints for your board, view the board documentation.

Version History

Introduced in R2015a