Hierarchy Flattening - MATLAB & Simulink (original) (raw)

What Is Hierarchy Flattening?

Hierarchy flattening enables you to remove subsystem hierarchy from the HDL code generated from your design.

HDL Coder™ considers blocks within a flattened subsystem to be at the same level of hierarchy, and no longer grouped into separate subsystems. This consideration allows the code generator to reorganize blocks for optimization across the original hierarchical boundaries, while preserving functionality.

When to Flatten Hierarchy

To preserve the modularity of the design and have a one-to-one mapping from subsystem name to corresponding HDL module orentity name, do not flatten the hierarchy. The generated HDL code is more readable when you don't flatten the hierarchy.

Flatten hierarchy to:

• Enable more extensive area and speed optimization.
• Reduce the number of HDL output files. For every subsystem that you flatten, HDL Coder generates one less HDL output file.

Considerations

• Before you flatten the hierarchy, you must have theMaskParameterAsGeneric property set tooff. For more information, see Generate parameterized HDL code from masked subsystem.
• When you use optimizations such as resource sharing or streaming with hierarchy flattening, in certain cases, HDL Coder might retain the subsystem hierarchy in the generated model. However, the HDL code generated for the flattened subsystems is inlined, which reduces the number of HDL files.
• When you use floating-point data types in Native Floating Point mode, HDL Coder might not flatten the hierarchy. This is because floating-point designs generate hundreds of lines of code and inlining the HDL files makes the generated code less readable.

How to Flatten Hierarchy

By default, a subsystem inherits its hierarchy flattening setting from the parent subsystem. However, you can enable or disable flattening for individual subsystems. This table lists options you can specify for hierarchy flattening options for a subsystem are listed in the following table.

To set hierarchy flattening using the HDL Block Properties dialog box:

• In the Apps tab, select HDL Coder. The HDL Code tab appears. Select theSubsystem and then click . For FlattenHierarchy, select , , or .
• Right-click the Subsystem and select > . ForFlattenHierarchy, select , , or .

To set hierarchy flattening from the command line, use hdlset_param. For example, to turn on hierarchy flattening for a subsystem, my_dut:

hdlset_param('my_dut', 'FlattenHierarchy', 'on')

See also hdlset_param.

Hierarchy Flattening Report

To see the hierarchy flattening information in the report, before you generate code for each subsystem or model reference, enable the optimization report. To enable this report, in the HDL Code tab, selectReport Options, and then select Generate optimization report.

The report displays subsystems in your model that haveFlattenHierarchy set to on andoff, hierarchy flattening status, and the HDL files that are inlined. You can use the report to more effectively flatten the subsystem hierarchy and improve opportunities for optimizations such as clock-rate pipelining on the model.

If hierarchy flattening is unsuccessful, the report shows a table that contains subsystems that are not flattened, and reasons for not flattening the subsystem. Subsystems that have a * highlighted beside it indicates whether the HDL files are inlined though hierarchy flattening failed.

Limitations for Hierarchy Flattening

A subsystem cannot be flattened if the subsystem is:

• A Synchronous Subsystem or uses the State Control block inSynchronous mode.
• A model reference implementation.
• A Triggered Subsystem when Use trigger signal as clock is enabled.

See Also

makehdl

Topics

• Clock-Rate Pipelining
• Resource Sharing
• Streaming
• Create and Use Code Generation Reports