Use importhdl function to import synthesizable Verilog® code into the Simulink® modeling environment. Make sure that the constructs used in the HDL code are supported by HDL import.
These tables list the supported Verilog constructs that you can use when you import your HDL code. If you use an unsupported construct, HDL import generates an error when parsing the input HDL file. Verilog HDL import can sometimes ignore the presence of certain constructs in the HDL code. To learn more, see the Comments section of the table.
Module Definition and Instantiations
Verilog Constructs
Supported?
Comments
Library declaration
No
–
Configuration declaration
No
–
Module declaration
Yes
Multiple sample rates and multiple clock inputs are not supported.
Module parameter port list
Yes
–
Port declarations
Yes
INOUT ports are not supported.
Module without ports
No
–
Local parameter declaration
Yes
–
Parameter declaration
Yes
You can use parameters and constants that have a maximum size of64 bits. By default, the parameter size is32 bits.
Module instantiation
Yes
Unconnected ports in the instantiated modules are removed when importing the Verilog code.Recursive module instantiation is not supported. Instead, if your top module instantiates modules that are defined in recursive subfolders, importhdl parses all Verilog files. For example, in this figure,importhdl can parse bothDFF_Instantiation.v andTFF_Instantiation.v that are instantiated inDFF.v.
Multiple sample rates and multiple clock signals are not supported.
Register inference
Yes
–
Compare to Constant block inference
Yes
–
Gain block inference
Yes
–
RAM inference
Yes
–
ROM inference
No
–
Counter inference
No
–
Drive strength
No
–
Limitations and Considerations
Verilog import does not support:
Importing of Verilog files from a read-only folder.
Generation of the preprocessing files in a read-only file system that parses the HDL code you input to the importhdl function.
Attribute instances and comments, which are ignored.
(#)delay values, such as #25, which are ignored.
Enumeration data types.
More than one clock signal.
Modules that are multirate.
Recursive module instantiation.
Multiport Switch inference with more than 1024 inputs. If you specify more than 1024 inputs to a Multiport Switch block that gets inferred from the Verilog code, Verilog import generates an error. The error is generated because the Simulink modeling environment does not support more than 1024 inputs for the block.
