FPGA-in-the-Loop Wizard - Generate an FPGA-in-the-loop (FIL) block or System object from existing HDL files - MATLAB (original) (raw)

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Generate an FPGA-in-the-loop (FIL) block or System object from existing HDL files

Description

FPGA-in-the-loop (FIL) enables you to run a Simulink® or MATLAB® simulation that is synchronized with an HDL design running on an AMD®, Microchip, or Altera® FPGA board.

This link between the simulator and the board enables you to:

• Verify HDL implementations directly against algorithms in Simulink or MATLAB.
• Apply data and test scenarios from Simulink or MATLAB to the HDL design on the FPGA.
• Integrate existing HDL code with models under development in Simulink or MATLAB.

Open the FPGA-in-the-Loop Wizard App

• Simulink Toolstrip: In the Apps tab, under Verification, Validation and Test, click the HDL Verifier icon. Select FPGA-in-the-Loop (FIL) on the left pane, and click Import HDL Files.
• MATLAB command prompt: EnterfilWizard. You provide the HDL code and all related information for creating a FIL block for simulation with an FPGA device.

Examples

• Block Generation with the FIL Wizard
• System Object Generation with the FIL Wizard

Programmatic Use

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filWizard(`filename`) relaunches the FIL Wizard using a configuration file from a previous session. At the end of each FIL Wizard session, the tool saves a MAT-file that contains the session information. You can use this MAT-file to restore the session later.

Version History

Introduced in R2012b