Execute Free-Running FPGA-in-the-Loop Using HDL Workflow Advisor - MATLAB & Simulink (original) (raw)

Generate Free-Running FIL Project

1. Follow instructions for invoking the HDL Workflow Advisor. See Getting Started with the HDL Workflow Advisor (HDL Coder).
   Note
   You must have an HDL Coder™ license to generate HDL code using the HDL Workflow Advisor.
2. In step 1.1. Set Target Device and Synthesis Tool:
   1. Set Target workflow toFPGA-in-the-Loop.
   2. Set Target platform to a supported board, for example, AMD Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. The HDL Workflow Advisor fills inFamily, Device,Package, and Speed. If you have not yet downloaded HDL Verifier™ Support Package for AMD FPGA and SoC Devices, select Get more boards. Then return to this step after you have downloaded the support package.
   3. For Project folder, enter the folder name to save the project files into. The default ishdl_prj under the current working folder.
   4. Click Run This Task.
3. In step 1.2. Set Target Frequency:
   1. Set the Target Frequency (MHz) for the clock speed of your design implemented on the FPGA. The available range of frequencies is shown in theFrequency Range (MHz) parameter. The HDL Workflow Advisor checks the requested frequency against those possible for the requested board. If the requested frequency is not possible for this board, Workflow Advisor returns an error and suggests an alternate frequency. For AMD® Vivado® supported boards, or PCI Express® boards, Workflow Advisor cannot check the frequency. The synthesis tools make a best effort attempt at the requested frequency but might choose an alternate frequency if the specified frequency was not achievable. The default is25 MHz.
   2. Click Run This Task.
4. In step 2. Prepare Model for HDL Code Generation, perform steps 2.1–2.2 as described in Prepare Model for HDL Code Generation Overview (HDL Coder).
5. In step 3. HDL Code Generation, perform steps 3.1–3.2 as described in HDL Code Generation Overview (HDL Coder).
6. In step 4.1. Set FPGA-in-the-Loop Options:
   1. Set theFPGA-in-the-Loop Connection method to a supported interface, for example, USB Ethernet. The options in the drop-down menu update depend on the connection methods supported for the target board you selected.
      Note
      Free-running FIL supportsEthernet and USB Ethernet interfaces only.
   2. Under MATLAB/FPGA Synchronization Mode, select Free-running FPGA.
      Note
      For free-running FIL, the HDL Workflow Advisor:
      • Does not generate the Simulink® verification model, as this mode works only when you use FIL with a MATLAB® System object™. It does not work when you use FIL with a Simulink block.
      • Always generates the host interface script.
   3. Under Specify additional source files for the HDL design, select additional source files for the HDL design that is to be verified on the FPGA board by usingAdd, if required. To (optionally) display the full paths to the source files, select the box titledShow full paths to source files. The HDL Workflow Advisor attempts to identify the file type. Change the file type in the File Type column if it is incorrect.
   4. Click Run This Task.
      
7. In the 4.2. Set DUT I/O Ports step:
   1. The HDL Workflow Advisor parses the input and output ports of your DUT from the top file. It infers each port type from the HDL port name. Verify and modify the port type as needed.
   2. Click Run This Task.
      
8. In the 4.3. Build FPGA-in-the-Loop step, to start the Vivado project build, click Run This Task. When the build is done, note the following artifacts in your working directory:
   • A project directory —fpgaproj
   • A bit file —_`DUTName`__fil.bit, where _`DUTName`_ is the name of the DUT
   • FIL class files —_`DUTName`__fil.m, where _`DUTName`_ is the name of the DUT
   • A host interface script —gs_ _`DUTName`__interface_fil.m, where _`DUTName`_ is the name of the DUT

Run FIL Simulation

Before you can run FIL with an FPGA board, you must configure the board and connect it to the host machine by using the Hardware Setup app.

To access help and a list of properties and methods for the free-running FIL class, enter the following command at the MATLAB command prompt:

The generated host interface script,gs_ _`DUTName`__interface_fil.m, creates a filObj object for interfacing with the FPGA from MATLAB. The interface script contains MATLAB commands that connect to the hardware and program the FPGA, and examples of how to exchange data with your algorithm as it runs on the hardware.

The host interface script performs these actions:

• Create FIL Object — The host interface script creates a custom free-running FIL object from the class definition file generated by the HDL Workflow Advisor.
  You can change writable properties as needed, for example:
  filObj.IPAddress = '192.168.1.101';
• Program FPGA — The host interface script uses this command to program the FPGA board:
• Send Data — The host interface script uses the writePort method to send data to DUT ports.
  You can send a sample data to one control data port. For example:
  filObj.writePort("ctrl",);
  "ctrl" is the name of input control data port and<ctrlValue> is the port value.
  You can send data to all streaming data ports. For example:
  filObj.writePort("din1",,"din2",);
  "din1" and "din2" are the names of input streaming data ports, and <din1Value> and<din2Value> are the port values, which must be the same length.
• Receive Data — The host interface script uses the readPort method to receive data from the DUT ports.
  To receive a frame, you must first specify the frame length.
  obj.ReadFrameLength = ;
  You can optionally specify a timeout for receiving data. Specify in units of seconds. The default value is 5 seconds.
  obj.TimeOut = ;
  You can receive data from all streaming data ports. For example:
  [dout1Value, dout2Value] = obj.readPort("dout1","dout2");
  "dout1" and "dout2" are the names of output streaming ports, and dout1Value anddout2Value are the received frame data.
  You can receive sample data from one control data port at a time. For example:
  statusValue = obj.readPort("status");
  "status" is the name of output control data port andstatusValue is the port value.
• Release Object — The host interface script uses this command to release the connection with the FPGA board.

See Also

Topics

• What Is Free-Running FPGA-in-the-Loop?