Zero-Order Hold - Implement zero-order hold sample period - Simulink (original) (raw)

Implement zero-order hold sample period

Libraries:
Simulink / Discrete
HDL Coder / Discrete

Description

The Zero-Order Hold block holds its input for the sample period you specify. If the input is a vector, the block holds all elements of the vector for the same sample period.

You specify the time between samples with the Sample time parameter. A setting of -1 means the block inherits theSample time.

Tip

Do not use the Zero-Order Hold block to create a fast-to-slow transition between blocks operating at different sample rates. Instead, use the Rate Transition block.

Bus Support

The Zero-Order Hold block is a bus-capable block. The input can be a virtual or nonvirtual bus signal. No block-specific restrictions exist. All signals in a nonvirtual bus input to a Zero-Order Hold block must have the same sample time, even if the elements of the associated bus object specify inherited sample times. You can use a Rate Transition block to change the sample time of an individual signal, or of all signals in a bus. See Modify Sample Times for Nonvirtual Buses andBus-Capable Blocks for more information.

You can use an array of buses as an input signal to a Zero-Order Hold block. For details about defining and using an array of buses, see Group Nonvirtual Buses in Arrays of Buses.

Comparison with Similar Blocks

The Memory, Unit Delay, and Zero-Order Hold blocks provide similar functionality but have different capabilities. Also, the purpose of each block is different.

This table shows recommended usage for each block.

Each block has the following capabilities.

Capability	Memory	Unit Delay	Zero-Order Hold
Specification of initial condition	Yes	Yes	No, because the block output at time t = 0 must match the input value.
Specification of sample time	No, because the block can only inherit sample time from the driving block or the solver used for the entire model.	Yes	Yes
Support for frame-based signals	No	Yes	Yes
Support for state logging	No	Yes	No

Examples

Ports

Input

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Input signal that the block holds by one sample period.

Output

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Output signal that is the input held by one sample period.

Parameters

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Specify the time interval between samples. To inherit the sample time, set this parameter to -1. See Specify Sample Time for more information.

Do not specify a continuous sample time (0 or[0,0]). This block supports only discrete sample times. When this parameter is -1, the inherited sample time must be discrete and not continuous.

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

To get the block parameter value programmatically, use the get_param function.

Parameter:	SampleTime
Values:	-1 (default) \| positive scalar number
Data Types:	char \| string

Example: set_param("mdl/Zero-Order Hold","SampleTime","0.1") specifies a discrete sample time of 0.1 for the Zero-Order Hold block named Zero-Order Hold in the model named mdl.

Block Characteristics

Data Types	Boolean \| bus	double	enumerated	fixed point	integer	single
Direct Feedthrough	yes
Multidimensional Signals	no
Variable-Size Signals	no
Zero-Crossing Detection	no

Extended Capabilities

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Generated code relies on memcpy or memset functions (strong.h) under certain conditions.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0. For more details, see OutputPipeline (HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

Version History

Introduced before R2006a