[LLVMdev] Match immediate value in tablegen (original) (raw)

Matt Arsenault Matthew.Arsenault at amd.com
Wed Jul 1 14:25:30 PDT 2015

On 07/01/2015 02:06 PM, Xiaochu Liu wrote:

I was trying to do a pattern matching for a rd+imm instruction in my own backend. It looks something like: def: Pat<buildvector v2i16:$src1, v2i16:$src2, (OR (SLLI GPR:_ _$src1,16), GPR:$src2>; OR takes two i32 in registers and SLLI takes one i32 in registers and an immediate.

But the immediate '16' does not work here and I tried different ways. May I know if any of you have any idea how to bake an immediate value (16) into the tablegen?

How specifically doesn't it work / what is the error? What version of LLVM are you using?How are SLLI's operands defined? -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150701/b5c3fa32/attachment.html>

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