[LLVMdev] How to select ISD::sdivrem node? (original) (raw)
Pei-Shiang Hung pshung807 at gmail.com
Wed Jul 8 02:53:56 PDT 2015
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Hello all,
I'm a novice to porting a new LLVM backend. My target has a native instruction named divrs which takes 2 input operands and produces 2 output results.
The format is divrs rt,rt, rt,rs, ra,ra, ra,rb
The operation of divrs is to divide rawithra with rawithrb, then put quotient into rtandremainderintort and remainder into rtandremainderintors.
Therefore, I think I can map ISD::sdivrem to my native instruction divrs directly. I define the following pattern.
def DIVSR : F32_ALU1_DIV<(outs GPR5:$rt, GPR5:$rs), (ins GPR5:$ra, GPR5:$rb), "divs", [(set i32:$rt, i32:$rs (sdivrem i32:$ra, i32:$rb))]>;
but, I get the following error message while running llvm-tblgen
llvm-tblgen: llvm/llvm_3.6.1/llvm-3.6.1.src/include/llvm/ADT/SmallVector.h:138: T& llvm::SmallVe ctorTemplateCommon<T,
::_operator[](llvm::SmallVectorTemplateCommon<T,_ >::size_type) [with T = llvm::EEVT::TypeSet; = void; llvm::SmallVectorTemplateCommon<T, >::reference = llvm::EEVT::TypeSet&; llvm::SmallVectorTemplateCommon<T, ::_sizetype = long unsigned int]: Assertion `idx < size()' failed._ #0 0x7fc0285d5036 llvm::sys::PrintStackTrace(_IO_FILE*) llvm/llvm_3.6.1/llvm-3.6.1.src/lib/Support/Unix/Signals.inc:423:0 #1 0x7fc0285d52e0 PrintStackTraceSignalHandler(void*) llvm/llvm_3.6.1/llvm-3.6.1.src/lib/Support /Unix/Signals.inc:481:0 #2 0x7fc0285d3dd3 SignalHandler(int) llvm/llvm_3.6.1/llvm-3.6.1.src/lib/Support/Unix/Signals.inc :_198:0_ #3 0x7fc0275b2b80 (/lib64/libc.so.6+0x33b80) #4 0x7fc0275b2b07 gsignal /var/tmp/portage/sys-libs/glibc-2.20-r2/work/glibc-2.20/signal/../sysdeps/unix/sysv/linux/raise.c:55:0 #5 0x7fc0275b3e9a abort /var/tmp/portage/sys-libs/glibc-2.20-r2/work/glibc-2.20/stdlib/abort.c:91:0 #6 0x7fc0275ab95d __assert_fail_base /var/tmp/portage/sys-libs/glibc-2.20-r2/work/glibc-2.20/assert/assert.c:92:0 #7 0x7fc0275aba12 (/lib64/libc.so.6+0x2ca12) #8 0x49b52d llvm::SmallVectorTemplateCommon<llvm::EEVT::TypeSet, void>::operator[](unsigned long) llvm/llvm_3.6.1/llvm-3.6.1.src/include/llvm/ADT/SmallVector.h:139:0 #9 0x485143 llvm::TreePatternNode::getExtType(unsigned int) llvm/llvm_3.6.1/llvm-3.6.1.src/utils /TableGen/CodeGenDAGPatterns.h:354:0 #10 0x496861 llvm::CodeGenDAGPatterns::parseInstructionPattern(llvm::CodeGenInstruction&, llvm::ListInit*, std::map<ll vm::Record*, llvm::DAGInstruction, llvm::LessRecordByID, std::allocator<std::pair<llvm::Record* const, llvm::DAGInstru ction> > >&) llvm/llvm_3.6.1/llvm-3.6.1.src/utils/TableGen/CodeGenDAGPatterns.cpp:2949:0 #11 0x496fe4 llvm::CodeGenDAGPatterns::ParseInstructions() llvm/llvm_3.6.1/llvm-3.6.1.src/utils/ TableGen/CodeGenDAGPatterns.cpp:3015:0
I'm not familiar of how llvm-tblgen generates patterns. Can someone tell me what's wrong?
Thanks for the information.
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