[LLVMdev] New backend help request. (original) (raw)

Tim Northover t.p.northover at gmail.com
Thu Jul 9 11:15:16 PDT 2015

As that just turns into stores, sets, etc. But how would you represent things like indexed access?

move dn, (an,dn) move dn, offset(an)

These are fairly easy (the difficulty with the pre/post indexed modes is that they tend to define two values or otherwise not be tree-like in DAG form).

For these you just put in a more complicated pattern representing the address calculation that happens. For example, with "(an, dn)" the address is "an+dn" so you'd write your pattern as: "(store i32:$Dn, (add i32:$An, i32:$Dm)". For the "Dn.W" variants you'll probably want to throw a trunc in there.

And for the offset ones you'll want to define an "offsetimm" (or whatever your preferred name is) instance of ImmLeaf with i32 type (because addresses are 32-bits) but only accepting signed 16-bit values that can actually be encoded:

def offsetimm : ImmLeaf<i32, [{ return Imm >= -32768 && Imm <= 32767; }]>; [...] (store i32:$Dn, (add i32:$An, offsetimm:$imm))

The biggest wrinkle is that you probably want to defer choosing whether to use An or Dn as the offset as long as possible. You could either fix that up later (optimisation!) or try to define these instructions to accept both Dn and An and then encode it properly. I'm afraid I don't know enough about the 68k instruction set to be sure which is better.

Cheers.

Tim.

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