[llvm-dev] How to add Loongson ISA for Mips target? (original) (raw)

Leslie Zhai via llvm-dev llvm-dev at lists.llvm.org
Thu Sep 6 09:13:31 PDT 2018

Hi Simon,

Thanks for your teaching!

As an apprentice in the backend,  I just followed AVRSubtarget and ARMSubtarget:

https://github.com/xiangzhai/llvm/commits?author=xiangzhai

So I thought there might also need Loongson3A subtarget:

https://en.wikipedia.org/wiki/Loongson#Loongson_3

I just copied the MipsInstrInfo.td and renamed to Loongson3AInstrInfo.td,  and implemented some load and store LoongExt64 instructions for ISA_LOONGSON class:

let AdditionalPredicates = [NotInMicroMips] in {   def GSLDLE   : LoadMemory<"gsldle", GPR64Opnd, mem_simmptr, load, II_GSLDLE>,                  LW_FM<0x16>, ISA_LOONGSON;   def GSLDGT   : LoadMemory<"gsldgt", GPR64Opnd, mem_simmptr, load, II_GSLDGT>,                  LW_FM<0x17>, ISA_LOONGSON;   def GSSDLE   : StoreMemory<"gssdle", GPR64Opnd, mem_simmptr, store, II_GSSDLE>,                  LW_FM<0x16>, ISA_LOONGSON;   def GSSDGT   : StoreMemory<"gssdgt", GPR64Opnd, mem_simmptr, store, II_GSSDGT>,                  LW_FM<0x17>, ISA_LOONGSON; }

There are about 14 load and store,  13 arithmetic && logic operations LoongExt64 instructions, not including LoongExt32 and binary translation ISA.

But I have a requirement:

在 2018年09月06日 19:01, Simon Atanasyan 写道:

Hi,

LLVM MIPS backend now supports different MIPS ISA like mips1, mips2, mips3, mips32, mips32r6 etc. If Loongson ISA just add a few new instructions I think you do not have to add a new subtarget. Take a look at MipsInstrInfo.td file. In that file there are multiple ISAMIPSxxx classes. Take for example ISAMIPS3 and search it through *.td files. Here is an example of instruction definition specific to mips3: [[ def DMTC1 : MTC1FT<"dmtc1", FGR64Opnd, GPR64Opnd, IIDMTC1,_ _bitconvert>, MFC1FM<5>, ISAMIPS3; ]] More general and complete guide can be found here: http://llvm.org/docs/WritingAnLLVMBackend.html On Thu, Sep 6, 2018 at 1:01 PM Leslie Zhai <zhaixiang at loongson.cn> wrote: Hi LLVM developers,

GCC[1] is able to use Loongson ISA[2] for instruction selection: $ cat hello.c #include <stdio.h> int main(int argc, char *argv[]) { printf("Hello World\n"); return 0; } $ gcc -O0 -S hello.c $ cat hello.s .file 1 "hello.c" .section .mdebug.abi64 .previous .nan legacy .gnuattribute 4, 1 .abicalls .rdata .align 3 .LC0: .ascii "Hello World\000" .text .align 2 .globl main .set nomips16 .set nomicromips .ent main .type main, @function main: .frame fp,48,fp,48,fp,48,31 # vars= 16, regs= 3/0, args= 0, gp= 0 .mask 0xd0000000,-8 .fmask 0x00000000,0 .set noreorder .set nomacro daddiu sp,sp,sp,sp,-48 gssq 31,31,31,fp,32($sp) sd 28,24(28,24(28,24(sp) move fp,fp,fp,sp lui $28,%hi(%neg(%gprel(main))) daddu 28,28,28,28,$25 daddiu 28,28,28,28,%lo(%neg(%gprel(main))) move 2,2,2,4 sd 5,8(5,8(5,8(fp) sll 2,2,2,2,0 sw 2,0(2,0(2,0(fp) ld 2,2,%gotpage(.LC0)(2,28) daddiu 4,4,4,2,%gotofst(.LC0) ld 2,2,%call16(puts)(2,28) move 25,25,25,2 .reloc 1f,RMIPSJALR,puts 1: jalr $25 nop move 2,2,2,0 move sp,sp,sp,fp gslq 31,31,31,fp,32($sp) ld 28,24(28,24(28,24(sp) daddiu sp,sp,sp,sp,48 j $31 nop .set macro .set reorder .end main .size main, .-main .ident "GCC: (GNU) 4.9.3 20150626 (Red Hat 4.9.3-8)" gssq and gslq are some instructions of Loongson ISA. How to add Loongson ISA for Mips target? I just: * add loongson3a cpu in frontend https://github.com/xiangzhai/clang/commits?author=xiangzhai * initial Loongson3A subtarget skeleton. Are there some documents or papers? Please teach me, thanks a lot! 1. https://github.com/loongson-community/gcc 2. Chinese Simplified version http://www.loongson.cn/uploadfile/cpu/3A3000/Loongson3A30003B3000user2.pdf

-- Regards, Leslie Zhai

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