[llvm-dev] [GlobalISel][MIPS] Legality and instruction combining (original) (raw)

Petar Avramovic via llvm-dev llvm-dev at lists.llvm.org
Mon Sep 17 08:08:42 PDT 2018

Thanks Daniel,

On 14.09.2018. 18:31, Daniel Sanders wrote:

On 14 Sep 2018, at 06:50, pavram <Petar.Avramovic at rt-rk.com_ _<mailto:Petar.Avramovic at rt-rk.com>> wrote:

We could get similar result if we have: getActionDefinitionsBuilder(GSELECT) .legalFor({{s32, s32}, {s64, s32}, {p0, s32}}) .clampScalar(0, s32, s64) .clampScalar(1, s32, s32) .widenScalarToNextPow2(0); And in this case sizes of LLTs and register classes would be the same. Implementation for GICMP on AArch64 is very similar to second described option for GSELECT. Is there a reason for different implementation of GSELECT and GICMP on AArch64? Are there some general ruses to determine which of the two given options is better in which case? At the moment, it largely comes down to preference. I don't have any real evidence to back this up but I expect the latter will be the better optimized in the long run since maintaining the excess bits requires instructions and these are explicit in the GMIR. This means we can optimize it and decline to do it whenever it doesn't matter. Then, for now, I will widen s1 to size of register class in instruction "to be selected". -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180917/792e0138/attachment.html>

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