[llvm-dev] Unmodeled side effects and scheduling latency (original) (raw)
Mattias Eriksson V via llvm-dev llvm-dev at lists.llvm.org
Mon Sep 24 09:22:30 PDT 2018
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Hi!
I Have a question on how to think about instructions marked with "hasSideEffects = 1" in the scheduler. In my out-of-tree back-end we recently had this situation:
SU(0): set_configuration_reg SU(1): read_from_memory
SU(0) is marked with "hasSideEffects = 1". ScheduleDAGInstrs::buildSchedGraph() considered there to be an order-dependency between the instructions, but set its latency to 0. So our custom VLIW scheduler put SU(0) and SU(1) in the same bundle. In reality the configuration register actually affects how the read behaves, so bundling these two caused a bug.
Is the scheduler correct in setting the latency to 0 correct in this case?
Mattias
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