[llvm-dev] i1 true ^= -1 in DAG matcher? (original) (raw)
Tim Northover via llvm-dev llvm-dev at lists.llvm.org
Wed Feb 19 11:10:52 PST 2020
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Hi Hendrik,
On Wed, 19 Feb 2020 at 11:01, Hendrik Greving via llvm-dev <llvm-dev at lists.llvm.org> wrote:
It looks like that in the DAG matcher, the DAG has a xor with '-1' for checking a true value vector
for instance, %cmp4.i = icmp ne <8 x i32> %6, %5 %7 = xor <8 x i1> %cmp4.i, <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true> [use of %7] results in vector of '-1' in the DAG.
This should be controlled by TargetLowering::setBooleanVectorContents, which lets each target choose whether a boolean is 0/1 or 0/-1 when held in a larger register. For AMDGPU it looks like R600 wants 0/-1, but SIL wants 0/1 so if you're seeing -1 when compiling for a SIL target that's probably a bug.
Cheers.
Tim.
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