[llvm-dev] Handling far branches with fixups or ELF relocs (original) (raw)
Denis Steckelmacher via llvm-dev llvm-dev at lists.llvm.org
Wed Jul 1 01:47:25 PDT 2020
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Hello,
I'm working on an LLVM backend for an experimental microprocessor. Work is going on nicely, and I've until now found the answer to all my questions directly in the LLVM source code, or in the documentation.
However, I'm having problems with the AsmBackend class and the handling of fixups.
The processor I'm working with has a single conditional branch instruction, JCC, that takes an IP-relative 9-bit immediate offset as operand. A second version of the instruction takes a register as operand and can therefore jump to any 32-bit address.
In AsmBackend, there are methods for relaxing instructions, that I wanted to use to replace "JCC imm9" instructions with a sequence of instructions that jumps further. However, I have two questions:
- relaxInstruction does not seem to be able to replace one instruction with a sequence of instructions
- I've looked at many other LLVM backends (AVR, ARC, ARM, MIPS and RISC-V), and none of them really seem to do interesting things in relaxInstruction. ARM for instance relaxes Thumb instructions to normal instructions, and RISC-V relaxes compressed instructions to normal ones too. But in both cases, even the normal instructions have limited range, for which there is an assertion, but no "solution" for when a branch exceeds the range of the instruction.
It therefore seems that the problem of "conditional branches that jump too far" is solved elsewhere, but I could not find that location. I looked at LLD, and I've seen that RISC-V has some code there (related to the PLT) that produces sequences of instructions, but not the other targets.
So, what would be the best way to change "JCC imm9" instructions to something else when a branch has to jump further than 256 instructions before or after the current one?
Best regards, Denis Steckelmacher
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