[llvm-dev] BPF tablegen+codegen question (original) (raw)

Chris Sears via llvm-dev llvm-dev at lists.llvm.org
Tue May 12 14:23:02 PDT 2020

In BPF, an ADD instruction is defined as a 2 register instruction:

    0x0f.  add dst, src.  dst += src

In BPFInstrInfo.td this kind of ALU instruction is defined with:

    def _rr : ALU_RR<BPF_ALU64, Opc,
               (outs GPR:$dst),
               (ins GPR:$src2, GPR:$src),
               "$dst "#OpcodeStr#" $src",
               [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;

How does tablegen+codegen ensure that dst and src2 are the same register? I see that the assembly/disassembly string assumes this is the case.

Also, it uses i64:$src which is an i64 and not a GPR. What is the distinction there? X86 does this differently. src1 and src2 are GR64 registers.

    def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
                               (ins GR64:$src1, GR64:$src2),
              "imul{q}\t{$src2, <span class="katex"><span class="katex-mathml"><math xmlns="http://www.w3.org/1998/Math/MathML"><semantics><mrow><mi>d</mi><mi>s</mi><mi>t</mi><mi mathvariant="normal">∣</mi></mrow><annotation encoding="application/x-tex">dst|</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:1em;vertical-align:-0.25em;"></span><span class="mord mathnormal">d</span><span class="mord mathnormal">s</span><span class="mord mathnormal">t</span><span class="mord">∣</span></span></span></span>dst, $src2}",
              [(set GR64:$dst, EFLAGS,
                    (X86smul_flag GR64:$src1, GR64:$src2))]>,
              Sched<[WriteIMul64Reg]>, TB;

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