AArch64AdvSIMDScalarPass.cpp Source File (original) (raw)

47using namespace llvm;

49#define DEBUG_TYPE "aarch64-simd-scalar"

55 cl::desc("Force use of AdvSIMD scalar instructions everywhere"),

58 STATISTIC(NumScalarInsnsUsed, "Number of scalar instructions used");

59 STATISTIC(NumCopiesDeleted, "Number of cross-class copies deleted");

60 STATISTIC(NumCopiesInserted, "Number of cross-class copies inserted");

62#define AARCH64_ADVSIMD_NAME "AdvSIMD Scalar Operation Optimization"

64namespace {

69private:

83public:

84 static char ID;

91 void getAnalysisUsage(AnalysisUsage &AU) const override {

94 }

95};

96char AArch64AdvSIMDScalar::ID = 0;

97}

101

102static bool isGPR64(unsigned Reg, unsigned SubReg,

105 return false;

107 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);

108 return AArch64::GPR64RegClass.contains(Reg);

109}

110

114 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&

116 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&

117 SubReg == AArch64::dsub);

118

120 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub);

121}

122

123

124

129

130 if (MI->getOpcode() == AArch64::FMOVDXr ||

131 MI->getOpcode() == AArch64::FMOVXDr)

132 return &MI->getOperand(1);

133

134

135 if (MI->getOpcode() == AArch64::UMOVvi64 && MI->getOperand(2).getImm() == 0) {

136 SubReg = AArch64::dsub;

137 return &MI->getOperand(1);

138 }

139

140

141 if (MI->getOpcode() == AArch64::COPY) {

142 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),

144 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI))

145 return &MI->getOperand(1);

146 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),

148 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(),

150 SubReg = MI->getOperand(1).getSubReg();

151 return &MI->getOperand(1);

152 }

153 }

154

155

156 return nullptr;

157}

158

159

160

161

163 switch (Opc) {

164 default:

165 break;

166

167 case AArch64::ADDXrr:

168 return AArch64::ADDv1i64;

169 case AArch64::SUBXrr:

170 return AArch64::SUBv1i64;

171 case AArch64::ANDXrr:

172 return AArch64::ANDv8i8;

173 case AArch64::EORXrr:

174 return AArch64::EORv8i8;

175 case AArch64::ORRXrr:

176 return AArch64::ORRv8i8;

177 }

178

179 return Opc;

180}

181

183 unsigned Opc = MI.getOpcode();

185}

186

187

188

189

190bool AArch64AdvSIMDScalar::isProfitableToTransform(

192

193

195 return false;

196

197

198

199 unsigned NumNewCopies = 3;

200 unsigned NumRemovableCopies = 0;

201

202 Register OrigSrc0 = MI.getOperand(1).getReg();

203 Register OrigSrc1 = MI.getOperand(2).getReg();

204 unsigned SubReg0;

205 unsigned SubReg1;

206 if ( MRI ->def_empty(OrigSrc0)) {

208 MRI->def_instr_begin(OrigSrc0);

209 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");

211

212 if (MOSrc0)

213 --NumNewCopies;

214

215

216 if (MOSrc0 && MRI->hasOneNonDBGUse(OrigSrc0))

217 ++NumRemovableCopies;

218 }

219 if ( MRI ->def_empty(OrigSrc1)) {

221 MRI->def_instr_begin(OrigSrc1);

222 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");

224 if (MOSrc1)

225 --NumNewCopies;

226

227

228 if (MOSrc1 && MRI->hasOneNonDBGUse(OrigSrc1))

229 ++NumRemovableCopies;

230 }

231

232

233

234

235

236

237 Register Dst = MI.getOperand(0).getReg();

238 bool AllUsesAreCopies = true;

240 Use = MRI->use_instr_nodbg_begin(Dst),

241 E = MRI->use_instr_nodbg_end();

242 Use != E; ++Use) {

245 ++NumRemovableCopies;

246

247

248

249

250

251 else if (Use->getOpcode() == AArch64::INSERT_SUBREG ||

252 Use->getOpcode() == AArch64::INSvi64gpr)

253 ;

254 else

255 AllUsesAreCopies = false;

256 }

257

258

259 if (AllUsesAreCopies)

260 --NumNewCopies;

261

262

263

264 if (NumNewCopies <= NumRemovableCopies)

265 return true;

266

267

268

270}

271

273 unsigned Dst, unsigned Src, bool IsKill) {

275 TII->get(AArch64::COPY), Dst)

278 ++NumCopiesInserted;

279 return MIB;

280}

281

282

283

284

285void AArch64AdvSIMDScalar::transformInstruction(MachineInstr &MI) {

287

288 MachineBasicBlock *MBB = MI.getParent();

289 unsigned OldOpc = MI.getOpcode();

291 assert(OldOpc != NewOpc && "transform an instruction to itself?!");

292

293

294 Register OrigSrc0 = MI.getOperand(1).getReg();

295 Register OrigSrc1 = MI.getOperand(2).getReg();

296 unsigned Src0 = 0, SubReg0;

297 unsigned Src1 = 0, SubReg1;

298 bool KillSrc0 = false, KillSrc1 = false;

299 if ( MRI ->def_empty(OrigSrc0)) {

301 MRI->def_instr_begin(OrigSrc0);

302 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");

304

305

306 if (MOSrc0) {

307 Src0 = MOSrc0->getReg();

308 KillSrc0 = MOSrc0->isKill();

309

311 if (MRI->hasOneNonDBGUse(OrigSrc0)) {

312 assert(MOSrc0 && "Can't delete copy w/o a valid original source!");

313 Def->eraseFromParent();

314 ++NumCopiesDeleted;

315 }

316 }

317 }

318 if ( MRI ->def_empty(OrigSrc1)) {

320 MRI->def_instr_begin(OrigSrc1);

321 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");

323

324

325 if (MOSrc1) {

326 Src1 = MOSrc1->getReg();

327 KillSrc1 = MOSrc1->isKill();

328

330 if (MRI->hasOneNonDBGUse(OrigSrc1)) {

331 assert(MOSrc1 && "Can't delete copy w/o a valid original source!");

332 Def->eraseFromParent();

333 ++NumCopiesDeleted;

334 }

335 }

336 }

337

338

339 if (!Src0) {

340 SubReg0 = 0;

341 Src0 = MRI->createVirtualRegister(&AArch64::FPR64RegClass);

343 KillSrc0 = true;

344 }

345 if (!Src1) {

346 SubReg1 = 0;

347 Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass);

349 KillSrc1 = true;

350 }

351

352

353

354

355 Register Dst = MRI->createVirtualRegister(&AArch64::FPR64RegClass);

356

357

358

359

363

364

365

366

368

369

370 MI.eraseFromParent();

371

372 ++NumScalarInsnsUsed;

373}

374

375

376bool AArch64AdvSIMDScalar::processMachineBasicBlock(MachineBasicBlock *MBB) {

380 transformInstruction(MI);

382 }

383 }

385}

386

387

388bool AArch64AdvSIMDScalar::runOnMachineFunction(MachineFunction &mf) {

390 LLVM_DEBUG(dbgs() << "***** AArch64AdvSIMDScalar *****\n");

391

393 return false;

394

397

398

399 for (MachineBasicBlock &MBB : mf)

400 if (processMachineBasicBlock(&MBB))

403}

404

405

406

408 return new AArch64AdvSIMDScalar();

409}

static cl::opt< bool > TransformAll("aarch64-a57-fp-load-balancing-force-all", cl::desc("Always modify dest registers regardless of color"), cl::init(false), cl::Hidden)

return AArch64::GPR64RegClass contains(Reg)

#define AARCH64_ADVSIMD_NAME

Definition AArch64AdvSIMDScalarPass.cpp:62

static MachineInstr * insertCopy(const TargetInstrInfo *TII, MachineInstr &MI, unsigned Dst, unsigned Src, bool IsKill)

Definition AArch64AdvSIMDScalarPass.cpp:272

static cl::opt< bool > TransformAll("aarch64-simd-scalar-force-all", cl::desc("Force use of AdvSIMD scalar instructions everywhere"), cl::init(false), cl::Hidden)

static bool isTransformable(const MachineInstr &MI)

Definition AArch64AdvSIMDScalarPass.cpp:182

unsigned SubReg

Definition AArch64AdvSIMDScalarPass.cpp:102

static unsigned getTransformOpcode(unsigned Opc)

Definition AArch64AdvSIMDScalarPass.cpp:162

unsigned const MachineRegisterInfo * MRI

Definition AArch64AdvSIMDScalarPass.cpp:103

static bool isFPR64(unsigned Reg, unsigned SubReg, const MachineRegisterInfo *MRI)

Definition AArch64AdvSIMDScalarPass.cpp:111

static MachineOperand * getSrcFromCopy(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &SubReg)

Definition AArch64AdvSIMDScalarPass.cpp:125

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

static bool isProfitableToTransform(const Loop &L, const BranchInst *BI)

Promote Memory to Register

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

Represent the analysis usage information of a pass.

LLVM_ABI void setPreservesCFG()

This function should be called by the pass, iff they do not:

FunctionPass class - This class is used to implement most global optimizations.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

void setIsKill(bool Val=true)

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

defusechain_instr_iterator< true, false, true, true > use_instr_nodbg_iterator

use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified r...

defusechain_instr_iterator< false, true, false, true > def_instr_iterator

def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register,...

static constexpr bool isVirtualRegister(unsigned Reg)

Return true if the specified register number is in the virtual register namespace.

StringRef - Represent a constant reference to a string, i.e.

TargetInstrInfo - Interface to description of machine instruction set.

virtual const TargetInstrInfo * getInstrInfo() const

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

initializer< Ty > init(const Ty &Val)

NodeAddr< DefNode * > Def

NodeAddr< UseNode * > Use

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)

Make a range that does early increment to allow mutation of the underlying range without disrupting i...

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

unsigned getKillRegState(bool B)

FunctionPass * createAArch64AdvSIMDScalar()

Definition AArch64AdvSIMDScalarPass.cpp:407