LLVM: lib/Target/AArch64/Utils/AArch64BaseInfo.h Source File (original) (raw)
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16#ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
17#define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
18
19
20
27
28namespace llvm {
29
31 switch (Reg.id()) {
32 case AArch64::X0: return AArch64::W0;
33 case AArch64::X1: return AArch64::W1;
34 case AArch64::X2: return AArch64::W2;
35 case AArch64::X3: return AArch64::W3;
36 case AArch64::X4: return AArch64::W4;
37 case AArch64::X5: return AArch64::W5;
38 case AArch64::X6: return AArch64::W6;
39 case AArch64::X7: return AArch64::W7;
40 case AArch64::X8: return AArch64::W8;
41 case AArch64::X9: return AArch64::W9;
42 case AArch64::X10: return AArch64::W10;
43 case AArch64::X11: return AArch64::W11;
44 case AArch64::X12: return AArch64::W12;
45 case AArch64::X13: return AArch64::W13;
46 case AArch64::X14: return AArch64::W14;
47 case AArch64::X15: return AArch64::W15;
48 case AArch64::X16: return AArch64::W16;
49 case AArch64::X17: return AArch64::W17;
50 case AArch64::X18: return AArch64::W18;
51 case AArch64::X19: return AArch64::W19;
52 case AArch64::X20: return AArch64::W20;
53 case AArch64::X21: return AArch64::W21;
54 case AArch64::X22: return AArch64::W22;
55 case AArch64::X23: return AArch64::W23;
56 case AArch64::X24: return AArch64::W24;
57 case AArch64::X25: return AArch64::W25;
58 case AArch64::X26: return AArch64::W26;
59 case AArch64::X27: return AArch64::W27;
60 case AArch64::X28: return AArch64::W28;
61 case AArch64::FP: return AArch64::W29;
62 case AArch64::LR: return AArch64::W30;
63 case AArch64::SP: return AArch64::WSP;
64 case AArch64::XZR: return AArch64::WZR;
65 }
66
67 return Reg;
68}
69
71 switch (Reg.id()) {
72 case AArch64::W0: return AArch64::X0;
73 case AArch64::W1: return AArch64::X1;
74 case AArch64::W2: return AArch64::X2;
75 case AArch64::W3: return AArch64::X3;
76 case AArch64::W4: return AArch64::X4;
77 case AArch64::W5: return AArch64::X5;
78 case AArch64::W6: return AArch64::X6;
79 case AArch64::W7: return AArch64::X7;
80 case AArch64::W8: return AArch64::X8;
81 case AArch64::W9: return AArch64::X9;
82 case AArch64::W10: return AArch64::X10;
83 case AArch64::W11: return AArch64::X11;
84 case AArch64::W12: return AArch64::X12;
85 case AArch64::W13: return AArch64::X13;
86 case AArch64::W14: return AArch64::X14;
87 case AArch64::W15: return AArch64::X15;
88 case AArch64::W16: return AArch64::X16;
89 case AArch64::W17: return AArch64::X17;
90 case AArch64::W18: return AArch64::X18;
91 case AArch64::W19: return AArch64::X19;
92 case AArch64::W20: return AArch64::X20;
93 case AArch64::W21: return AArch64::X21;
94 case AArch64::W22: return AArch64::X22;
95 case AArch64::W23: return AArch64::X23;
96 case AArch64::W24: return AArch64::X24;
97 case AArch64::W25: return AArch64::X25;
98 case AArch64::W26: return AArch64::X26;
99 case AArch64::W27: return AArch64::X27;
100 case AArch64::W28: return AArch64::X28;
101 case AArch64::W29: return AArch64::FP;
102 case AArch64::W30: return AArch64::LR;
103 case AArch64::WSP: return AArch64::SP;
104 case AArch64::WZR: return AArch64::XZR;
105 }
106
107 return Reg;
108}
109
111 switch (RegTuple.id()) {
112 case AArch64::X0_X1_X2_X3_X4_X5_X6_X7: return AArch64::X0;
113 case AArch64::X2_X3_X4_X5_X6_X7_X8_X9: return AArch64::X2;
114 case AArch64::X4_X5_X6_X7_X8_X9_X10_X11: return AArch64::X4;
115 case AArch64::X6_X7_X8_X9_X10_X11_X12_X13: return AArch64::X6;
116 case AArch64::X8_X9_X10_X11_X12_X13_X14_X15: return AArch64::X8;
117 case AArch64::X10_X11_X12_X13_X14_X15_X16_X17: return AArch64::X10;
118 case AArch64::X12_X13_X14_X15_X16_X17_X18_X19: return AArch64::X12;
119 case AArch64::X14_X15_X16_X17_X18_X19_X20_X21: return AArch64::X14;
120 case AArch64::X16_X17_X18_X19_X20_X21_X22_X23: return AArch64::X16;
121 case AArch64::X18_X19_X20_X21_X22_X23_X24_X25: return AArch64::X18;
122 case AArch64::X20_X21_X22_X23_X24_X25_X26_X27: return AArch64::X20;
123 case AArch64::X22_X23_X24_X25_X26_X27_X28_FP: return AArch64::X22;
124 }
125
126 return RegTuple;
127}
128
130 switch (Reg.id()) {
131 case AArch64::D0: return AArch64::B0;
132 case AArch64::D1: return AArch64::B1;
133 case AArch64::D2: return AArch64::B2;
134 case AArch64::D3: return AArch64::B3;
135 case AArch64::D4: return AArch64::B4;
136 case AArch64::D5: return AArch64::B5;
137 case AArch64::D6: return AArch64::B6;
138 case AArch64::D7: return AArch64::B7;
139 case AArch64::D8: return AArch64::B8;
140 case AArch64::D9: return AArch64::B9;
141 case AArch64::D10: return AArch64::B10;
142 case AArch64::D11: return AArch64::B11;
143 case AArch64::D12: return AArch64::B12;
144 case AArch64::D13: return AArch64::B13;
145 case AArch64::D14: return AArch64::B14;
146 case AArch64::D15: return AArch64::B15;
147 case AArch64::D16: return AArch64::B16;
148 case AArch64::D17: return AArch64::B17;
149 case AArch64::D18: return AArch64::B18;
150 case AArch64::D19: return AArch64::B19;
151 case AArch64::D20: return AArch64::B20;
152 case AArch64::D21: return AArch64::B21;
153 case AArch64::D22: return AArch64::B22;
154 case AArch64::D23: return AArch64::B23;
155 case AArch64::D24: return AArch64::B24;
156 case AArch64::D25: return AArch64::B25;
157 case AArch64::D26: return AArch64::B26;
158 case AArch64::D27: return AArch64::B27;
159 case AArch64::D28: return AArch64::B28;
160 case AArch64::D29: return AArch64::B29;
161 case AArch64::D30: return AArch64::B30;
162 case AArch64::D31: return AArch64::B31;
163 }
164
165 return Reg;
166}
167
169 switch (Reg.id()) {
170 case AArch64::B0: return AArch64::D0;
171 case AArch64::B1: return AArch64::D1;
172 case AArch64::B2: return AArch64::D2;
173 case AArch64::B3: return AArch64::D3;
174 case AArch64::B4: return AArch64::D4;
175 case AArch64::B5: return AArch64::D5;
176 case AArch64::B6: return AArch64::D6;
177 case AArch64::B7: return AArch64::D7;
178 case AArch64::B8: return AArch64::D8;
179 case AArch64::B9: return AArch64::D9;
180 case AArch64::B10: return AArch64::D10;
181 case AArch64::B11: return AArch64::D11;
182 case AArch64::B12: return AArch64::D12;
183 case AArch64::B13: return AArch64::D13;
184 case AArch64::B14: return AArch64::D14;
185 case AArch64::B15: return AArch64::D15;
186 case AArch64::B16: return AArch64::D16;
187 case AArch64::B17: return AArch64::D17;
188 case AArch64::B18: return AArch64::D18;
189 case AArch64::B19: return AArch64::D19;
190 case AArch64::B20: return AArch64::D20;
191 case AArch64::B21: return AArch64::D21;
192 case AArch64::B22: return AArch64::D22;
193 case AArch64::B23: return AArch64::D23;
194 case AArch64::B24: return AArch64::D24;
195 case AArch64::B25: return AArch64::D25;
196 case AArch64::B26: return AArch64::D26;
197 case AArch64::B27: return AArch64::D27;
198 case AArch64::B28: return AArch64::D28;
199 case AArch64::B29: return AArch64::D29;
200 case AArch64::B30: return AArch64::D30;
201 case AArch64::B31: return AArch64::D31;
202 }
203
204 return Reg;
205}
206
208 switch (Opcode) {
209 case AArch64::LDADDAB: case AArch64::LDADDAH:
210 case AArch64::LDADDAW: case AArch64::LDADDAX:
211 case AArch64::LDADDALB: case AArch64::LDADDALH:
212 case AArch64::LDADDALW: case AArch64::LDADDALX:
213 case AArch64::LDCLRAB: case AArch64::LDCLRAH:
214 case AArch64::LDCLRAW: case AArch64::LDCLRAX:
215 case AArch64::LDCLRALB: case AArch64::LDCLRALH:
216 case AArch64::LDCLRALW: case AArch64::LDCLRALX:
217 case AArch64::LDEORAB: case AArch64::LDEORAH:
218 case AArch64::LDEORAW: case AArch64::LDEORAX:
219 case AArch64::LDEORALB: case AArch64::LDEORALH:
220 case AArch64::LDEORALW: case AArch64::LDEORALX:
221 case AArch64::LDSETAB: case AArch64::LDSETAH:
222 case AArch64::LDSETAW: case AArch64::LDSETAX:
223 case AArch64::LDSETALB: case AArch64::LDSETALH:
224 case AArch64::LDSETALW: case AArch64::LDSETALX:
225 case AArch64::LDSMAXAB: case AArch64::LDSMAXAH:
226 case AArch64::LDSMAXAW: case AArch64::LDSMAXAX:
227 case AArch64::LDSMAXALB: case AArch64::LDSMAXALH:
228 case AArch64::LDSMAXALW: case AArch64::LDSMAXALX:
229 case AArch64::LDSMINAB: case AArch64::LDSMINAH:
230 case AArch64::LDSMINAW: case AArch64::LDSMINAX:
231 case AArch64::LDSMINALB: case AArch64::LDSMINALH:
232 case AArch64::LDSMINALW: case AArch64::LDSMINALX:
233 case AArch64::LDUMAXAB: case AArch64::LDUMAXAH:
234 case AArch64::LDUMAXAW: case AArch64::LDUMAXAX:
235 case AArch64::LDUMAXALB: case AArch64::LDUMAXALH:
236 case AArch64::LDUMAXALW: case AArch64::LDUMAXALX:
237 case AArch64::LDUMINAB: case AArch64::LDUMINAH:
238 case AArch64::LDUMINAW: case AArch64::LDUMINAX:
239 case AArch64::LDUMINALB: case AArch64::LDUMINALH:
240 case AArch64::LDUMINALW: case AArch64::LDUMINALX:
241 case AArch64::SWPAB: case AArch64::SWPAH:
242 case AArch64::SWPAW: case AArch64::SWPAX:
243 case AArch64::SWPALB: case AArch64::SWPALH:
244 case AArch64::SWPALW: case AArch64::SWPALX:
245 return true;
246 }
247 return false;
248}
249
251
252
253
271
273
274
279};
280
282 switch (Code) {
284 case EQ: return "eq";
285 case NE: return "ne";
286 case HS: return "hs";
287 case LO: return "lo";
288 case MI: return "mi";
289 case PL: return "pl";
290 case VS: return "vs";
291 case VC: return "vc";
292 case HI: return "hi";
293 case LS: return "ls";
294 case GE: return "ge";
295 case LT: return "lt";
296 case GT: return "gt";
297 case LE: return "le";
298 case AL: return "al";
299 case NV: return "nv";
300 }
301}
302
304
305
306 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
307}
308
309
310
311
313 switch (CC) {
314 default:
315 return AL;
316 case EQ:
317 return EQ;
318 case NE:
319 return NE;
320 case HS:
321 return LS;
322 case LO:
323 return HI;
324 case HI:
325 return LO;
326 case LS:
327 return HS;
328 case GE:
329 return LE;
330 case LT:
331 return GT;
332 case GT:
333 return LT;
334 case LE:
335 return GE;
336 }
337}
338
339
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342
344
345 enum { N = 8, Z = 4, C = 2, V = 1 };
346 switch (Code) {
348 case EQ: return Z;
349 case NE: return 0;
351 case LO: return 0;
353 case PL: return 0;
354 case VS: return V;
355 case VC: return 0;
357 case LS: return 0;
358 case GE: return 0;
360 case GT: return 0;
361 case LE: return Z;
362 }
363}
364
365
366
368 switch (Code) {
369 default:
370 return false;
381 return true;
382 }
383}
384
385}
386
391
395
397 return ActiveFeatures[llvm::AArch64::FeatureAll] ||
399 }
400
402};
403
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429
430namespace AArch64SVCR {
434#define GET_SVCRValues_DECL
435#define GET_SVCRsList_DECL
436#include "AArch64GenSystemOperands.inc"
437}
438
443#define GET_ATValues_DECL
444#define GET_ATsList_DECL
445#include "AArch64GenSystemOperands.inc"
446}
447
452#define GET_DBValues_DECL
453#define GET_DBsList_DECL
454#include "AArch64GenSystemOperands.inc"
455}
456
461#define GET_DBnXSValues_DECL
462#define GET_DBnXSsList_DECL
463#include "AArch64GenSystemOperands.inc"
464}
465
470#define GET_DCValues_DECL
471#define GET_DCsList_DECL
472#include "AArch64GenSystemOperands.inc"
473}
474
479#define GET_ICValues_DECL
480#define GET_ICsList_DECL
481#include "AArch64GenSystemOperands.inc"
482}
483
488#define GET_ISBValues_DECL
489#define GET_ISBsList_DECL
490#include "AArch64GenSystemOperands.inc"
491}
492
497#define GET_TSBValues_DECL
498#define GET_TSBsList_DECL
499#include "AArch64GenSystemOperands.inc"
500}
501
506#define GET_PRFMValues_DECL
507#define GET_PRFMsList_DECL
508#include "AArch64GenSystemOperands.inc"
509}
510
515#define GET_SVEPRFMValues_DECL
516#define GET_SVEPRFMsList_DECL
517#include "AArch64GenSystemOperands.inc"
518}
519
524#define GET_RPRFMValues_DECL
525#define GET_RPRFMsList_DECL
526#include "AArch64GenSystemOperands.inc"
527}
528
534#define GET_SVEPREDPATValues_DECL
535#define GET_SVEPREDPATsList_DECL
536#include "AArch64GenSystemOperands.inc"
537}
538
544#define GET_SVEVECLENSPECIFIERValues_DECL
545#define GET_SVEVECLENSPECIFIERsList_DECL
546#include "AArch64GenSystemOperands.inc"
547}
548
549
550
553 default:
554 return 0;
555 case AArch64SVEPredPattern::vl1:
556 case AArch64SVEPredPattern::vl2:
557 case AArch64SVEPredPattern::vl3:
558 case AArch64SVEPredPattern::vl4:
559 case AArch64SVEPredPattern::vl5:
560 case AArch64SVEPredPattern::vl6:
561 case AArch64SVEPredPattern::vl7:
562 case AArch64SVEPredPattern::vl8:
564 case AArch64SVEPredPattern::vl16:
565 return 16;
566 case AArch64SVEPredPattern::vl32:
567 return 32;
568 case AArch64SVEPredPattern::vl64:
569 return 64;
570 case AArch64SVEPredPattern::vl128:
571 return 128;
572 case AArch64SVEPredPattern::vl256:
573 return 256;
574 }
575}
576
577
578inline std::optional
580 switch (MinNumElts) {
581 default:
582 return std::nullopt;
583 case 1:
584 case 2:
585 case 3:
586 case 4:
587 case 5:
588 case 6:
589 case 7:
590 case 8:
591 return MinNumElts;
592 case 16:
593 return AArch64SVEPredPattern::vl16;
594 case 32:
595 return AArch64SVEPredPattern::vl32;
596 case 64:
597 return AArch64SVEPredPattern::vl64;
598 case 128:
599 return AArch64SVEPredPattern::vl128;
600 case 256:
601 return AArch64SVEPredPattern::vl256;
602 }
603}
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631#define GET_ExactFPImmValues_DECL
632#define GET_ExactFPImmsList_DECL
633#include "AArch64GenSystemOperands.inc"
634}
635
640#define GET_PStateImm0_15Values_DECL
641#define GET_PStateImm0_15sList_DECL
642#include "AArch64GenSystemOperands.inc"
643
647#define GET_PStateImm0_1Values_DECL
648#define GET_PStateImm0_1sList_DECL
649#include "AArch64GenSystemOperands.inc"
650}
651
656#define GET_PSBValues_DECL
657#define GET_PSBsList_DECL
658#include "AArch64GenSystemOperands.inc"
659}
660
666
668 return ActiveFeatures[llvm::AArch64::FeatureAll] ||
670 }
671};
672
673#define GET_PHintValues_DECL
674#define GET_PHintsList_DECL
675#include "AArch64GenSystemOperands.inc"
676
679}
680
685#define GET_BTIValues_DECL
686#define GET_BTIsList_DECL
687#include "AArch64GenSystemOperands.inc"
688}
689
694#define GET_CMHPRIORITYHINT_DECL
695#include "AArch64GenSystemOperands.inc"
696}
697
702#define GET_TINDEX_DECL
703#include "AArch64GenSystemOperands.inc"
704}
705
713
734
756
757inline static const char *
759 switch (Layout) {
773 }
774}
775
793
794namespace AArch64SysReg {
801
803 return ActiveFeatures[llvm::AArch64::FeatureAll] ||
805 }
806 };
807
808#define GET_SysRegsList_DECL
809#define GET_SysRegValues_DECL
810#include "AArch64GenSystemOperands.inc"
811
814}
815
820#define GET_TLBITable_DECL
821#include "AArch64GenSystemOperands.inc"
822}
823
828#define GET_TLBIPTable_DECL
829#include "AArch64GenSystemOperands.inc"
830}
831
836#define GET_MLBITable_DECL
837#include "AArch64GenSystemOperands.inc"
838}
839
844#define GET_GICTable_DECL
845#include "AArch64GenSystemOperands.inc"
846}
847
852#define GET_GICRTable_DECL
853#include "AArch64GenSystemOperands.inc"
854}
855
860#define GET_GSBTable_DECL
861#include "AArch64GenSystemOperands.inc"
862}
863
868#define GET_PLBITable_DECL
869#include "AArch64GenSystemOperands.inc"
870}
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960};
961}
962
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977
979 switch (KeyID) {
988 }
990}
991
992
993inline static std::optionalAArch64PACKey::ID
995 if (Name == "ia")
997 if (Name == "ib")
999 if (Name == "da")
1001 if (Name == "db")
1003 return std::nullopt;
1004}
1005
1006inline static unsigned getBTIHintNum(bool CallTarget, bool JumpTarget) {
1007 unsigned HintNum = 32;
1008 if (CallTarget)
1009 HintNum |= 2;
1010 if (JumpTarget)
1011 HintNum |= 4;
1012 assert(HintNum != 32 && "No target kinds!");
1013 return HintNum;
1014}
1015
1016namespace AArch64 {
1017
1018
1019
1020
1021
1022
1023
1026}
1027}
1028
1029#endif
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
#define LLVM_DECLARE_ENUM_AS_BITMASK(Enum, LargestValue)
LLVM_DECLARE_ENUM_AS_BITMASK can be used to declare an enum type as a bit set, so that bitwise operat...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Container class for subtarget features.
Wrapper class representing physical registers. Should be passed by value.
constexpr unsigned id() const
StringRef - Represent a constant reference to a string, i.e.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition AArch64BaseInfo.h:250
static bool isValidCBCond(AArch64CC::CondCode Code)
True, if a given condition code can be used in a fused compare-and-branch instructions,...
Definition AArch64BaseInfo.h:367
static CondCode getSwappedCondition(CondCode CC)
getSwappedCondition - assume the flags are set by MI(a,b), return the condition code if we modify the...
Definition AArch64BaseInfo.h:312
CondCode
Definition AArch64BaseInfo.h:254
@ VC
Definition AArch64BaseInfo.h:262
@ NONE_ACTIVE
Definition AArch64BaseInfo.h:278
@ NE
Definition AArch64BaseInfo.h:256
@ GE
Definition AArch64BaseInfo.h:265
@ PL
Definition AArch64BaseInfo.h:260
@ LAST_ACTIVE
Definition AArch64BaseInfo.h:277
@ EQ
Definition AArch64BaseInfo.h:255
@ HS
Definition AArch64BaseInfo.h:257
@ MI
Definition AArch64BaseInfo.h:259
@ GT
Definition AArch64BaseInfo.h:267
@ LT
Definition AArch64BaseInfo.h:266
@ VS
Definition AArch64BaseInfo.h:261
@ HI
Definition AArch64BaseInfo.h:263
@ FIRST_ACTIVE
Definition AArch64BaseInfo.h:276
@ LO
Definition AArch64BaseInfo.h:258
@ AL
Definition AArch64BaseInfo.h:269
@ ANY_ACTIVE
Definition AArch64BaseInfo.h:275
@ LE
Definition AArch64BaseInfo.h:268
@ Invalid
Definition AArch64BaseInfo.h:272
@ NV
Definition AArch64BaseInfo.h:270
@ LS
Definition AArch64BaseInfo.h:264
static const char * getCondCodeName(CondCode Code)
Definition AArch64BaseInfo.h:281
static CondCode getInvertedCondCode(CondCode Code)
Definition AArch64BaseInfo.h:303
static unsigned getNZCVToSatisfyCondCode(CondCode Code)
Given a condition code, return NZCV flags that would satisfy that condition.
Definition AArch64BaseInfo.h:343
Definition AArch64BaseInfo.h:872
TOF
Target Operand Flag enum.
Definition AArch64BaseInfo.h:874
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition AArch64BaseInfo.h:937
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
Definition AArch64BaseInfo.h:926
@ MO_G1
MO_G1 - A symbol operand with this flag (granule 1) represents the bits 16-31 of a 64-bit address,...
Definition AArch64BaseInfo.h:902
@ MO_S
MO_S - Indicates that the bits of the symbol operand represented by MO_G0 etc are signed.
Definition AArch64BaseInfo.h:941
@ MO_PAGEOFF
MO_PAGEOFF - A symbol operand with this flag represents the offset of that symbol within a 4K page.
Definition AArch64BaseInfo.h:890
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
Definition AArch64BaseInfo.h:921
@ MO_FRAGMENT
Definition AArch64BaseInfo.h:880
@ MO_NO_FLAG
Definition AArch64BaseInfo.h:878
@ MO_PREL
MO_PREL - Indicates that the bits of the symbol operand represented by MO_G0 etc are PC relative.
Definition AArch64BaseInfo.h:945
@ MO_G0
MO_G0 - A symbol operand with this flag (granule 0) represents the bits 0-15 of a 64-bit address,...
Definition AArch64BaseInfo.h:906
@ MO_ARM64EC_CALLMANGLE
MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version of a symbol,...
Definition AArch64BaseInfo.h:959
@ MO_PAGE
MO_PAGE - A symbol operand with this flag represents the pc-relative offset of the 4K page containing...
Definition AArch64BaseInfo.h:885
@ MO_HI12
MO_HI12 - This flag indicates that a symbol operand represents the bits 13-24 of a 64-bit address,...
Definition AArch64BaseInfo.h:911
@ MO_TLS
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
Definition AArch64BaseInfo.h:932
@ MO_G2
MO_G2 - A symbol operand with this flag (granule 2) represents the bits 32-47 of a 64-bit address,...
Definition AArch64BaseInfo.h:898
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
Definition AArch64BaseInfo.h:953
@ MO_G3
MO_G3 - A symbol operand with this flag (granule 3) represents the high 16-bits of a 64-bit address,...
Definition AArch64BaseInfo.h:894
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition AArch64BaseInfo.h:916
Definition AArch64BaseInfo.h:735
VectorLayout
Definition AArch64BaseInfo.h:736
@ VL_1D
Definition AArch64BaseInfo.h:741
@ VL_B
Definition AArch64BaseInfo.h:750
@ VL_8B
Definition AArch64BaseInfo.h:738
@ VL_4S
Definition AArch64BaseInfo.h:745
@ VL_2S
Definition AArch64BaseInfo.h:740
@ VL_4H
Definition AArch64BaseInfo.h:739
@ VL_16B
Definition AArch64BaseInfo.h:743
@ VL_2D
Definition AArch64BaseInfo.h:746
@ Invalid
Definition AArch64BaseInfo.h:737
@ VL_D
Definition AArch64BaseInfo.h:753
@ VL_S
Definition AArch64BaseInfo.h:752
@ VL_H
Definition AArch64BaseInfo.h:751
@ VL_8H
Definition AArch64BaseInfo.h:744
Definition AArch64BaseInfo.h:967
ID
Definition AArch64BaseInfo.h:968
@ IB
Definition AArch64BaseInfo.h:970
@ DA
Definition AArch64BaseInfo.h:971
@ LAST
Definition AArch64BaseInfo.h:973
@ DB
Definition AArch64BaseInfo.h:972
@ IA
Definition AArch64BaseInfo.h:969
const PHint * lookupPHintByName(StringRef)
const PHint * lookupPHintByEncoding(uint16_t)
Definition AArch64BaseInfo.h:714
ShiftExtSpecifiers
Definition AArch64BaseInfo.h:715
@ UXTB
Definition AArch64BaseInfo.h:723
@ SXTH
Definition AArch64BaseInfo.h:729
@ UXTH
Definition AArch64BaseInfo.h:724
@ MSL
Definition AArch64BaseInfo.h:718
@ SXTW
Definition AArch64BaseInfo.h:730
@ UXTX
Definition AArch64BaseInfo.h:726
@ LSL
Definition AArch64BaseInfo.h:717
@ ROR
Definition AArch64BaseInfo.h:721
@ SXTB
Definition AArch64BaseInfo.h:728
@ LSR
Definition AArch64BaseInfo.h:719
@ SXTX
Definition AArch64BaseInfo.h:731
@ Invalid
Definition AArch64BaseInfo.h:716
@ ASR
Definition AArch64BaseInfo.h:720
@ UXTW
Definition AArch64BaseInfo.h:725
Definition AArch64BaseInfo.h:706
ToggleCondition
Definition AArch64BaseInfo.h:707
@ Always
Definition AArch64BaseInfo.h:708
@ IfCallerIsNonStreaming
Definition AArch64BaseInfo.h:710
@ IfCallerIsStreaming
Definition AArch64BaseInfo.h:709
uint32_t parseGenericRegister(StringRef Name)
std::string genericRegisterString(uint32_t Bits)
static constexpr unsigned SVEMaxBitsPerVector
Definition AArch64BaseInfo.h:1025
static constexpr unsigned SVEBitsPerBlock
Definition AArch64BaseInfo.h:1024
@ C
The default llvm calling convention, compatible with C.
This is an optimization pass for GlobalISel generic memory operations.
static std::optional< AArch64PACKey::ID > AArch64StringToPACKeyID(StringRef Name)
Return numeric key ID for 2-letter identifier string.
Definition AArch64BaseInfo.h:994
TailFoldingOpts
An enum to describe what types of loops we should attempt to tail-fold: Disabled: None Reductions: Lo...
Definition AArch64BaseInfo.h:614
@ Simple
Definition AArch64BaseInfo.h:616
@ Reverse
Definition AArch64BaseInfo.h:619
@ Reductions
Definition AArch64BaseInfo.h:617
@ Recurrences
Definition AArch64BaseInfo.h:618
static unsigned getBTIHintNum(bool CallTarget, bool JumpTarget)
Definition AArch64BaseInfo.h:1006
static AArch64Layout::VectorLayout AArch64StringToVectorLayout(StringRef LayoutStr)
Definition AArch64BaseInfo.h:777
static const char * AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout)
Definition AArch64BaseInfo.h:758
std::optional< unsigned > getSVEPredPatternFromNumElements(unsigned MinNumElts)
Return specific VL predicate pattern based on the number of elements.
Definition AArch64BaseInfo.h:579
static bool atomicBarrierDroppedOnZero(unsigned Opcode)
Definition AArch64BaseInfo.h:207
static MCRegister getXRegFromWReg(MCRegister Reg)
Definition AArch64BaseInfo.h:70
static MCRegister getXRegFromXRegTuple(MCRegister RegTuple)
Definition AArch64BaseInfo.h:110
static MCRegister getWRegFromXReg(MCRegister Reg)
Definition AArch64BaseInfo.h:30
unsigned getNumElementsFromSVEPredPattern(unsigned Pattern)
Return the number of active elements for VL1 to VL256 predicate pattern, zero for all other patterns.
Definition AArch64BaseInfo.h:551
static MCRegister getDRegFromBReg(MCRegister Reg)
Definition AArch64BaseInfo.h:168
@ Disabled
Don't do any conversion of .debug_str_offsets tables.
static MCRegister getBRegFromDReg(MCRegister Reg)
Definition AArch64BaseInfo.h:129
static StringRef AArch64PACKeyIDToString(AArch64PACKey::ID KeyID)
Return 2-letter identifier string for numeric key ID.
Definition AArch64BaseInfo.h:978
Definition AArch64BaseInfo.h:440
constexpr SysAlias(const char *N, uint16_t E)
Definition AArch64BaseInfo.h:392
Definition AArch64BaseInfo.h:682
constexpr SysAlias(const char *N, uint16_t E)
Definition AArch64BaseInfo.h:392
Definition AArch64BaseInfo.h:691
constexpr SysAlias(const char *N, uint16_t E)
Definition AArch64BaseInfo.h:392
Definition AArch64BaseInfo.h:449
constexpr SysAlias(const char *N, uint16_t E)
Definition AArch64BaseInfo.h:392
Definition AArch64BaseInfo.h:458
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
Definition AArch64BaseInfo.h:424
Definition AArch64BaseInfo.h:467
constexpr SysAlias(const char *N, uint16_t E)
Definition AArch64BaseInfo.h:392
Definition AArch64BaseInfo.h:627
int Enum
Definition AArch64BaseInfo.h:628
const char * Repr
Definition AArch64BaseInfo.h:629
Definition AArch64BaseInfo.h:849
constexpr SysAliasReg(const char *N, uint16_t E, bool R)
Definition AArch64BaseInfo.h:406
Definition AArch64BaseInfo.h:841
constexpr SysAliasReg(const char *N, uint16_t E, bool R)
Definition AArch64BaseInfo.h:406
Definition AArch64BaseInfo.h:857
constexpr SysAlias(const char *N, uint16_t E)
Definition AArch64BaseInfo.h:392
Definition AArch64BaseInfo.h:476
constexpr SysAliasReg(const char *N, uint16_t E, bool R)
Definition AArch64BaseInfo.h:406
Definition AArch64BaseInfo.h:485
constexpr SysAlias(const char *N, uint16_t E)
Definition AArch64BaseInfo.h:392
Definition AArch64BaseInfo.h:833
constexpr SysAliasReg(const char *N, uint16_t E, bool R)
Definition AArch64BaseInfo.h:406
Definition AArch64BaseInfo.h:662
const char * Name
Definition AArch64BaseInfo.h:663
bool haveFeatures(FeatureBitset ActiveFeatures) const
Definition AArch64BaseInfo.h:667
unsigned Encoding
Definition AArch64BaseInfo.h:664
FeatureBitset FeaturesRequired
Definition AArch64BaseInfo.h:665
Definition AArch64BaseInfo.h:865
constexpr SysAliasOptionalReg(const char *N, uint16_t E, bool R, bool O)
Definition AArch64BaseInfo.h:415
Definition AArch64BaseInfo.h:503
constexpr SysAlias(const char *N, uint16_t E)
Definition AArch64BaseInfo.h:392
Definition AArch64BaseInfo.h:653
constexpr SysAlias(const char *N, uint16_t E)
Definition AArch64BaseInfo.h:392
Definition AArch64BaseInfo.h:637
constexpr SysAlias(const char *N, uint16_t E)
Definition AArch64BaseInfo.h:392
Definition AArch64BaseInfo.h:644
constexpr SysAlias(const char *N, uint16_t E)
Definition AArch64BaseInfo.h:392
Definition AArch64BaseInfo.h:521
constexpr SysAlias(const char *N, uint16_t E)
Definition AArch64BaseInfo.h:392
Definition AArch64BaseInfo.h:431
constexpr SysAlias(const char *N, uint16_t E)
Definition AArch64BaseInfo.h:392
Definition AArch64BaseInfo.h:512
constexpr SysAlias(const char *N, uint16_t E)
Definition AArch64BaseInfo.h:392
Definition AArch64BaseInfo.h:530
uint16_t Encoding
Definition AArch64BaseInfo.h:532
const char * Name
Definition AArch64BaseInfo.h:531
Definition AArch64BaseInfo.h:540
const char * Name
Definition AArch64BaseInfo.h:541
uint16_t Encoding
Definition AArch64BaseInfo.h:542
Definition AArch64BaseInfo.h:795
FeatureBitset FeaturesRequired
Definition AArch64BaseInfo.h:800
unsigned Encoding
Definition AArch64BaseInfo.h:797
bool Writeable
Definition AArch64BaseInfo.h:799
bool Readable
Definition AArch64BaseInfo.h:798
bool haveFeatures(FeatureBitset ActiveFeatures) const
Definition AArch64BaseInfo.h:802
const char Name[32]
Definition AArch64BaseInfo.h:796
Definition AArch64BaseInfo.h:699
constexpr SysAlias(const char *N, uint16_t E)
Definition AArch64BaseInfo.h:392
Definition AArch64BaseInfo.h:825
constexpr SysAliasOptionalReg(const char *N, uint16_t E, bool R, bool O)
Definition AArch64BaseInfo.h:415
Definition AArch64BaseInfo.h:817
constexpr SysAliasOptionalReg(const char *N, uint16_t E, bool R, bool O)
Definition AArch64BaseInfo.h:415
Definition AArch64BaseInfo.h:494
constexpr SysAlias(const char *N, uint16_t E)
Definition AArch64BaseInfo.h:392
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
Definition AArch64BaseInfo.h:424
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F)
Definition AArch64BaseInfo.h:426
uint16_t ImmValue
Definition AArch64BaseInfo.h:423
bool OptionalReg
Definition AArch64BaseInfo.h:414
bool NeedsReg
Definition AArch64BaseInfo.h:413
constexpr SysAliasOptionalReg(const char *N, uint16_t E, bool R, bool O, FeatureBitset F)
Definition AArch64BaseInfo.h:417
constexpr SysAliasOptionalReg(const char *N, uint16_t E, bool R, bool O)
Definition AArch64BaseInfo.h:415
constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F)
Definition AArch64BaseInfo.h:408
constexpr SysAliasReg(const char *N, uint16_t E, bool R)
Definition AArch64BaseInfo.h:406
bool NeedsReg
Definition AArch64BaseInfo.h:405
bool haveFeatures(FeatureBitset ActiveFeatures) const
Definition AArch64BaseInfo.h:396
constexpr SysAlias(const char *N, uint16_t E)
Definition AArch64BaseInfo.h:392
FeatureBitset getRequiredFeatures() const
Definition AArch64BaseInfo.h:401
const char * Name
Definition AArch64BaseInfo.h:388
FeatureBitset FeaturesRequired
Definition AArch64BaseInfo.h:390
constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)
Definition AArch64BaseInfo.h:393
uint16_t Encoding
Definition AArch64BaseInfo.h:389