AArch64CondBrTuning.cpp Source File (original) (raw)

41using namespace llvm;

43#define DEBUG_TYPE "aarch64-cond-br-tuning"

44#define AARCH64_CONDBR_TUNING_NAME "AArch64 Conditional Branch Tuning"

46namespace {

53public:

54 static char ID;

56 void getAnalysisUsage(AnalysisUsage &AU) const override;

60private:

63 bool Is64Bit);

66};

67}

69char AArch64CondBrTuning::ID = 0;

74void AArch64CondBrTuning::getAnalysisUsage(AnalysisUsage &AU) const {

75 AU.setPreservesCFG();

77}

81 return nullptr;

82 return MRI->getUniqueVRegDef(MO.getReg());

83}

85MachineInstr *AArch64CondBrTuning::convertToFlagSetting(MachineInstr &MI,

86 bool IsFlagSetting,

87 bool Is64Bit) {

90 if (IsFlagSetting) {

91 for (MachineOperand &MO : MI.implicit_operands())

94 return &MI;

95 }

96 unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode());

97 Register NewDestReg = MI.getOperand(0).getReg();

98 if (MRI->hasOneNonDBGUse(MI.getOperand(0).getReg()))

99 NewDestReg = Is64Bit ? AArch64::XZR : AArch64::WZR;

100

101 MachineInstrBuilder MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),

102 TII->get(NewOpc), NewDestReg);

103

104

105

106 if (MI.peekDebugInstrNum() != 0)

108

110 MIB.add(MO);

111

112 return MIB;

113}

114

115MachineInstr *AArch64CondBrTuning::convertToCondBr(MachineInstr &MI) {

118 switch (MI.getOpcode()) {

119 default:

121

122 case AArch64::CBZW:

123 case AArch64::CBZX:

125 break;

126 case AArch64::CBNZW:

127 case AArch64::CBNZX:

129 break;

130 case AArch64::TBZW:

131 case AArch64::TBZX:

133 break;

134 case AArch64::TBNZW:

135 case AArch64::TBNZX:

137 break;

138 }

139 return BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(AArch64::Bcc))

142}

143

144bool AArch64CondBrTuning::tryToTuneBranch(MachineInstr &MI,

145 MachineInstr &DefMI) {

146

147 if (MI.getParent() != DefMI.getParent())

148 return false;

149

150 bool IsFlagSetting = true;

151 unsigned MIOpc = MI.getOpcode();

152 MachineInstr *NewCmp = nullptr, *NewBr = nullptr;

153 switch (DefMI.getOpcode()) {

154 default:

155 return false;

156 case AArch64::ADDWri:

157 case AArch64::ADDWrr:

158 case AArch64::ADDWrs:

159 case AArch64::ADDWrx:

160 case AArch64::ANDWri:

161 case AArch64::ANDWrr:

162 case AArch64::ANDWrs:

163 case AArch64::BICWrr:

164 case AArch64::BICWrs:

165 case AArch64::SUBWri:

166 case AArch64::SUBWrr:

167 case AArch64::SUBWrs:

168 case AArch64::SUBWrx:

169 IsFlagSetting = false;

170 [[fallthrough]];

171 case AArch64::ADDSWri:

172 case AArch64::ADDSWrr:

173 case AArch64::ADDSWrs:

174 case AArch64::ADDSWrx:

175 case AArch64::ANDSWri:

176 case AArch64::ANDSWrr:

177 case AArch64::ANDSWrs:

178 case AArch64::BICSWrr:

179 case AArch64::BICSWrs:

180 case AArch64::SUBSWri:

181 case AArch64::SUBSWrr:

182 case AArch64::SUBSWrs:

183 case AArch64::SUBSWrx:

184 switch (MIOpc) {

185 default:

187

188 case AArch64::CBZW:

189 case AArch64::CBNZW:

190 case AArch64::TBZW:

191 case AArch64::TBNZW:

192

193 if ((MIOpc == AArch64::TBZW || MIOpc == AArch64::TBNZW) &&

194 MI.getOperand(1).getImm() != 31)

195 return false;

196

197

198

200 return false;

205

206 NewCmp = convertToFlagSetting(DefMI, IsFlagSetting, false);

207 NewBr = convertToCondBr(MI);

208 break;

209 }

210 break;

211

212 case AArch64::ADDXri:

213 case AArch64::ADDXrr:

214 case AArch64::ADDXrs:

215 case AArch64::ADDXrx:

216 case AArch64::ANDXri:

217 case AArch64::ANDXrr:

218 case AArch64::ANDXrs:

219 case AArch64::BICXrr:

220 case AArch64::BICXrs:

221 case AArch64::SUBXri:

222 case AArch64::SUBXrr:

223 case AArch64::SUBXrs:

224 case AArch64::SUBXrx:

225 IsFlagSetting = false;

226 [[fallthrough]];

227 case AArch64::ADDSXri:

228 case AArch64::ADDSXrr:

229 case AArch64::ADDSXrs:

230 case AArch64::ADDSXrx:

231 case AArch64::ANDSXri:

232 case AArch64::ANDSXrr:

233 case AArch64::ANDSXrs:

234 case AArch64::BICSXrr:

235 case AArch64::BICSXrs:

236 case AArch64::SUBSXri:

237 case AArch64::SUBSXrr:

238 case AArch64::SUBSXrs:

239 case AArch64::SUBSXrx:

240 switch (MIOpc) {

241 default:

243

244 case AArch64::CBZX:

245 case AArch64::CBNZX:

246 case AArch64::TBZX:

247 case AArch64::TBNZX: {

248

249 if ((MIOpc == AArch64::TBZX || MIOpc == AArch64::TBNZX) &&

250 MI.getOperand(1).getImm() != 63)

251 return false;

252

253

255 return false;

260

261 NewCmp = convertToFlagSetting(DefMI, IsFlagSetting, true);

262 NewBr = convertToCondBr(MI);

263 break;

264 }

265 }

266 break;

267 }

268 (void)NewCmp; (void)NewBr;

269 assert(NewCmp && NewBr && "Expected new instructions.");

270

275

276

277

278

279 if (!IsFlagSetting)

280 DefMI.eraseFromParent();

281 MI.eraseFromParent();

282 return true;

283}

284

285bool AArch64CondBrTuning::runOnMachineFunction(MachineFunction &MF) {

287 return false;

288

290 dbgs() << "********** AArch64 Conditional Branch Tuning **********\n"

291 << "********** Function: " << MF.getName() << '\n');

292

293 TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());

296

298 for (MachineBasicBlock &MBB : MF) {

299 bool LocalChange = false;

301 switch (MI.getOpcode()) {

302 default:

303 break;

304 case AArch64::CBZW:

305 case AArch64::CBZX:

306 case AArch64::CBNZW:

307 case AArch64::CBNZX:

308 case AArch64::TBZW:

309 case AArch64::TBZX:

310 case AArch64::TBNZW:

311 case AArch64::TBNZX:

312 MachineInstr *DefMI = getOperandDef(MI.getOperand(0));

313 LocalChange = (DefMI && tryToTuneBranch(MI, *DefMI));

314 break;

315 }

316

317

318 if (LocalChange) {

320 break;

321 }

322 }

323 }

325}

326

328 return new AArch64CondBrTuning();

329}

unsigned const MachineRegisterInfo * MRI

#define AARCH64_CONDBR_TUNING_NAME

Definition AArch64CondBrTuning.cpp:44

MachineInstrBuilder MachineInstrBuilder & DefMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

Promote Memory to Register

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

Represent the analysis usage information of a pass.

FunctionPass class - This class is used to implement most global optimizations.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

iterator_range< iterator > terminators()

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

Representation of each machine instruction.

void setDebugInstrNum(unsigned Num)

Set instruction number of this MachineInstr.

LLVM_ABI void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const

Print this MI to OS.

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

void setIsDead(bool Val=true)

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

virtual void print(raw_ostream &OS, const Module *M) const

print - Print out the internal state of the pass.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

StringRef - Represent a constant reference to a string, i.e.

virtual MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This is an optimization pass for GlobalISel generic memory operations.

auto drop_begin(T &&RangeOrContainer, size_t N=1)

Return a range covering RangeOrContainer with the first N elements excluded.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

FunctionPass * createAArch64CondBrTuning()

Definition AArch64CondBrTuning.cpp:327

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI, const MachineInstr &UseMI, const TargetRegisterInfo *TRI)

Return true if there is an instruction /after/ DefMI and before UseMI which either reads or clobbers ...