AArch64Disassembler.cpp Source File (original) (raw)

28#include

30using namespace llvm;

33#define DEBUG_TYPE "aarch64-disassembler"

38template

42#define Success MCDisassembler::Success

43#define Fail MCDisassembler::Fail

44#define SoftFail MCDisassembler::SoftFail

46template <unsigned RegClassID, unsigned FirstReg, unsigned NumRegsInClass>

50 if (RegNo > NumRegsInClass - 1)

54 AArch64MCRegisterClasses[RegClassID].getRegister(RegNo + FirstReg);

57}

62 if (RegNo > 22)

64 if (RegNo & 1)

68 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(

69 RegNo >> 1);

72}

74template <unsigned Min, unsigned Max>

78 unsigned Reg = (RegNo * 2) + Min;

82 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(Reg);

85}

87template <unsigned Min, unsigned Max>

90 const void *Decoder) {

91 unsigned Reg = (RegNo * 2) + Min;

96 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(Reg);

99}

100

103 if (RegNo > 7)

105

107 AArch64MCRegisterClasses[AArch64::ZPR_KRegClassID].getRegister(RegNo);

110}

111

114 const void *Decoder) {

115 if (RegNo * 4 > 28)

118 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);

121}

122

127 if (RegMask > 0xFF)

131}

132

138

144

150

155 AArch64MCRegisterClasses[AArch64::MPR16RegClassID].getRegister(RegNo);

158}

159

164 AArch64MCRegisterClasses[AArch64::MPR32RegClassID].getRegister(RegNo);

167}

168

173 AArch64MCRegisterClasses[AArch64::MPR64RegClassID].getRegister(RegNo);

176}

177

182 AArch64MCRegisterClasses[AArch64::MPR128RegClassID].getRegister(RegNo);

185}

186

189 const void *Decoder) {

190 if ((RegNo * 2) > 14)

193 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);

196}

197

201

202 Imm |= 0x20;

205}

206

213

217

218

220 if (ImmVal > (1 << 16))

222 ImmVal = -ImmVal;

224 false, 0, 0, 4))

227}

228

233

235 Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4))

238}

239

243

245 true, 0, 0, 4))

248}

249

257

267

275

279

280

284

285 if (IsToVec) {

287 Inst, Rd, Address, Decoder);

289 Inst, Rn, Address, Decoder);

290 } else {

292 Inst, Rd, Address, Decoder);

294 Inst, Rn, Address, Decoder);

295 }

296

297

299

301}

302

308

314

320

326

332

338

344

350

356

362

368

374

380

389 unsigned shift = (shiftHi << 6) | shiftLo;

391 default:

393 case AArch64::ADDWrs:

394 case AArch64::ADDSWrs:

395 case AArch64::SUBWrs:

396 case AArch64::SUBSWrs:

397

398 if (shiftHi == 0x3)

400 [[fallthrough]];

401 case AArch64::ANDWrs:

402 case AArch64::ANDSWrs:

403 case AArch64::BICWrs:

404 case AArch64::BICSWrs:

405 case AArch64::ORRWrs:

406 case AArch64::ORNWrs:

407 case AArch64::EORWrs:

408 case AArch64::EONWrs: {

409

410 if (shiftLo >> 5 == 1)

413 Decoder);

415 Decoder);

417 Decoder);

418 break;

419 }

420 case AArch64::ADDXrs:

421 case AArch64::ADDSXrs:

422 case AArch64::SUBXrs:

423 case AArch64::SUBSXrs:

424

425 if (shiftHi == 0x3)

427 [[fallthrough]];

428 case AArch64::ANDXrs:

429 case AArch64::ANDSXrs:

430 case AArch64::BICXrs:

431 case AArch64::BICSXrs:

432 case AArch64::ORRXrs:

433 case AArch64::ORNXrs:

434 case AArch64::EORXrs:

435 case AArch64::EONXrs:

437 Decoder);

439 Decoder);

441 Decoder);

442 break;

443 }

444

447}

448

455 shift <<= 4;

457 default:

459 case AArch64::MOVZWi:

460 case AArch64::MOVNWi:

461 case AArch64::MOVKWi:

462 if (shift & (1U << 5))

465 Decoder);

466 break;

467 case AArch64::MOVZXi:

468 case AArch64::MOVNXi:

469 case AArch64::MOVKXi:

471 Decoder);

472 break;

473 }

474

475 if (Inst.getOpcode() == AArch64::MOVKWi ||

476 Inst.getOpcode() == AArch64::MOVKXi)

478

480 0, 4))

482

485}

486

493

495 default:

497 case AArch64::PRFMui:

498

500 break;

501 case AArch64::STRBBui:

502 case AArch64::LDRBBui:

503 case AArch64::LDRSBWui:

504 case AArch64::STRHHui:

505 case AArch64::LDRHHui:

506 case AArch64::LDRSHWui:

507 case AArch64::STRWui:

508 case AArch64::LDRWui:

510 Decoder);

511 break;

512 case AArch64::LDRSBXui:

513 case AArch64::LDRSHXui:

514 case AArch64::LDRSWui:

515 case AArch64::STRXui:

516 case AArch64::LDRXui:

518 Decoder);

519 break;

520 case AArch64::LDRQui:

521 case AArch64::STRQui:

523 Decoder);

524 break;

525 case AArch64::LDRDui:

526 case AArch64::STRDui:

528 Decoder);

529 break;

530 case AArch64::LDRSui:

531 case AArch64::STRSui:

533 Decoder);

534 break;

535 case AArch64::LDRHui:

536 case AArch64::STRHui:

538 Decoder);

539 break;

540 case AArch64::LDRBui:

541 case AArch64::STRBui:

543 Decoder);

544 break;

545 }

546

548 Decoder);

552}

553

560

561

563 default:

564 break;

565 case AArch64::LDRSBWpre:

566 case AArch64::LDRSHWpre:

567 case AArch64::STRBBpre:

568 case AArch64::LDRBBpre:

569 case AArch64::STRHHpre:

570 case AArch64::LDRHHpre:

571 case AArch64::STRWpre:

572 case AArch64::LDRWpre:

573 case AArch64::LDRSBWpost:

574 case AArch64::LDRSHWpost:

575 case AArch64::STRBBpost:

576 case AArch64::LDRBBpost:

577 case AArch64::STRHHpost:

578 case AArch64::LDRHHpost:

579 case AArch64::STRWpost:

580 case AArch64::LDRWpost:

581 case AArch64::LDRSBXpre:

582 case AArch64::LDRSHXpre:

583 case AArch64::STRXpre:

584 case AArch64::LDRSWpre:

585 case AArch64::LDRXpre:

586 case AArch64::LDRSBXpost:

587 case AArch64::LDRSHXpost:

588 case AArch64::STRXpost:

589 case AArch64::LDRSWpost:

590 case AArch64::LDRXpost:

591 case AArch64::LDRQpre:

592 case AArch64::STRQpre:

593 case AArch64::LDRQpost:

594 case AArch64::STRQpost:

595 case AArch64::LDRDpre:

596 case AArch64::STRDpre:

597 case AArch64::LDRDpost:

598 case AArch64::STRDpost:

599 case AArch64::LDRSpre:

600 case AArch64::STRSpre:

601 case AArch64::LDRSpost:

602 case AArch64::STRSpost:

603 case AArch64::LDRHpre:

604 case AArch64::STRHpre:

605 case AArch64::LDRHpost:

606 case AArch64::STRHpost:

607 case AArch64::LDRBpre:

608 case AArch64::STRBpre:

609 case AArch64::LDRBpost:

610 case AArch64::STRBpost:

612 Decoder);

613 break;

614 }

615

617 default:

619 case AArch64::PRFUMi:

620

622 break;

623 case AArch64::STURBBi:

624 case AArch64::LDURBBi:

625 case AArch64::LDURSBWi:

626 case AArch64::STURHHi:

627 case AArch64::LDURHHi:

628 case AArch64::LDURSHWi:

629 case AArch64::STURWi:

630 case AArch64::LDURWi:

631 case AArch64::LDTRSBWi:

632 case AArch64::LDTRSHWi:

633 case AArch64::STTRWi:

634 case AArch64::LDTRWi:

635 case AArch64::STTRHi:

636 case AArch64::LDTRHi:

637 case AArch64::LDTRBi:

638 case AArch64::STTRBi:

639 case AArch64::LDRSBWpre:

640 case AArch64::LDRSHWpre:

641 case AArch64::STRBBpre:

642 case AArch64::LDRBBpre:

643 case AArch64::STRHHpre:

644 case AArch64::LDRHHpre:

645 case AArch64::STRWpre:

646 case AArch64::LDRWpre:

647 case AArch64::LDRSBWpost:

648 case AArch64::LDRSHWpost:

649 case AArch64::STRBBpost:

650 case AArch64::LDRBBpost:

651 case AArch64::STRHHpost:

652 case AArch64::LDRHHpost:

653 case AArch64::STRWpost:

654 case AArch64::LDRWpost:

655 case AArch64::STLURBi:

656 case AArch64::STLURHi:

657 case AArch64::STLURWi:

658 case AArch64::LDAPURBi:

659 case AArch64::LDAPURSBWi:

660 case AArch64::LDAPURHi:

661 case AArch64::LDAPURSHWi:

662 case AArch64::LDAPURi:

664 Decoder);

665 break;

666 case AArch64::LDURSBXi:

667 case AArch64::LDURSHXi:

668 case AArch64::LDURSWi:

669 case AArch64::STURXi:

670 case AArch64::LDURXi:

671 case AArch64::LDTRSBXi:

672 case AArch64::LDTRSHXi:

673 case AArch64::LDTRSWi:

674 case AArch64::STTRXi:

675 case AArch64::LDTRXi:

676 case AArch64::LDRSBXpre:

677 case AArch64::LDRSHXpre:

678 case AArch64::STRXpre:

679 case AArch64::LDRSWpre:

680 case AArch64::LDRXpre:

681 case AArch64::LDRSBXpost:

682 case AArch64::LDRSHXpost:

683 case AArch64::STRXpost:

684 case AArch64::LDRSWpost:

685 case AArch64::LDRXpost:

686 case AArch64::LDAPURSWi:

687 case AArch64::LDAPURSHXi:

688 case AArch64::LDAPURSBXi:

689 case AArch64::STLURXi:

690 case AArch64::LDAPURXi:

692 Decoder);

693 break;

694 case AArch64::LDURQi:

695 case AArch64::STURQi:

696 case AArch64::LDRQpre:

697 case AArch64::STRQpre:

698 case AArch64::LDRQpost:

699 case AArch64::STRQpost:

701 Decoder);

702 break;

703 case AArch64::LDURDi:

704 case AArch64::STURDi:

705 case AArch64::LDRDpre:

706 case AArch64::STRDpre:

707 case AArch64::LDRDpost:

708 case AArch64::STRDpost:

710 Decoder);

711 break;

712 case AArch64::LDURSi:

713 case AArch64::STURSi:

714 case AArch64::LDRSpre:

715 case AArch64::STRSpre:

716 case AArch64::LDRSpost:

717 case AArch64::STRSpost:

719 Decoder);

720 break;

721 case AArch64::LDURHi:

722 case AArch64::STURHi:

723 case AArch64::LDRHpre:

724 case AArch64::STRHpre:

725 case AArch64::LDRHpost:

726 case AArch64::STRHpost:

728 Decoder);

729 break;

730 case AArch64::LDURBi:

731 case AArch64::STURBi:

732 case AArch64::LDRBpre:

733 case AArch64::STRBpre:

734 case AArch64::LDRBpost:

735 case AArch64::STRBpost:

737 Decoder);

738 break;

739 }

740

742 Decoder);

744

748

749

750 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)

752

754}

755

763

764 unsigned Opcode = Inst.getOpcode();

765 switch (Opcode) {

766 default:

768 case AArch64::STLXRW:

769 case AArch64::STLXRB:

770 case AArch64::STLXRH:

771 case AArch64::STXRW:

772 case AArch64::STXRB:

773 case AArch64::STXRH:

775 Decoder);

776 [[fallthrough]];

777 case AArch64::LDARW:

778 case AArch64::LDARB:

779 case AArch64::LDARH:

780 case AArch64::LDAXRW:

781 case AArch64::LDAXRB:

782 case AArch64::LDAXRH:

783 case AArch64::LDXRW:

784 case AArch64::LDXRB:

785 case AArch64::LDXRH:

786 case AArch64::STLRW:

787 case AArch64::STLRB:

788 case AArch64::STLRH:

789 case AArch64::STLLRW:

790 case AArch64::STLLRB:

791 case AArch64::STLLRH:

792 case AArch64::LDLARW:

793 case AArch64::LDLARB:

794 case AArch64::LDLARH:

796 Decoder);

797 break;

798 case AArch64::STLXRX:

799 case AArch64::STXRX:

801 Decoder);

802 [[fallthrough]];

803 case AArch64::LDARX:

804 case AArch64::LDAXRX:

805 case AArch64::LDXRX:

806 case AArch64::STLRX:

807 case AArch64::LDLARX:

808 case AArch64::STLLRX:

810 Decoder);

811 break;

812 case AArch64::STLXPW:

813 case AArch64::STXPW:

815 Decoder);

816 [[fallthrough]];

817 case AArch64::LDAXPW:

818 case AArch64::LDXPW:

820 Decoder);

822 Decoder);

823 break;

824 case AArch64::STLXPX:

825 case AArch64::STXPX:

827 Decoder);

828 [[fallthrough]];

829 case AArch64::LDAXPX:

830 case AArch64::LDXPX:

832 Decoder);

834 Decoder);

835 break;

836 }

837

839 Decoder);

840

841

842 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||

843 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&

844 Rt == Rt2)

846

848}

849

858

859 unsigned Opcode = Inst.getOpcode();

860 bool NeedsDisjointWritebackTransfer = false;

861

862

863 switch (Opcode) {

864 default:

865 break;

866 case AArch64::LDPXpost:

867 case AArch64::STPXpost:

868 case AArch64::LDPSWpost:

869 case AArch64::LDPXpre:

870 case AArch64::STPXpre:

871 case AArch64::LDPSWpre:

872 case AArch64::LDPWpost:

873 case AArch64::STPWpost:

874 case AArch64::LDPWpre:

875 case AArch64::STPWpre:

876 case AArch64::LDPQpost:

877 case AArch64::STPQpost:

878 case AArch64::LDPQpre:

879 case AArch64::STPQpre:

880 case AArch64::LDPDpost:

881 case AArch64::STPDpost:

882 case AArch64::LDPDpre:

883 case AArch64::STPDpre:

884 case AArch64::LDPSpost:

885 case AArch64::STPSpost:

886 case AArch64::LDPSpre:

887 case AArch64::STPSpre:

888 case AArch64::STGPpre:

889 case AArch64::STGPpost:

890 case AArch64::LDTPpre:

891 case AArch64::LDTPpost:

892 case AArch64::LDTPQpost:

893 case AArch64::LDTPQpre:

894 case AArch64::STTPpost:

895 case AArch64::STTPpre:

896 case AArch64::STTPQpost:

897 case AArch64::STTPQpre:

899 Decoder);

900 break;

901 }

902

903 switch (Opcode) {

904 default:

906 case AArch64::LDPXpost:

907 case AArch64::STPXpost:

908 case AArch64::LDPSWpost:

909 case AArch64::LDPXpre:

910 case AArch64::STPXpre:

911 case AArch64::LDPSWpre:

912 case AArch64::STGPpre:

913 case AArch64::STGPpost:

914 case AArch64::LDTPpost:

915 case AArch64::LDTPpre:

916 case AArch64::STTPpost:

917 case AArch64::STTPpre:

918 NeedsDisjointWritebackTransfer = true;

919 [[fallthrough]];

920 case AArch64::LDNPXi:

921 case AArch64::STNPXi:

922 case AArch64::LDPXi:

923 case AArch64::STPXi:

924 case AArch64::LDPSWi:

925 case AArch64::STGPi:

926 case AArch64::LDTPi:

927 case AArch64::STTPi:

928 case AArch64::STTNPXi:

929 case AArch64::LDTNPXi:

931 Decoder);

933 Decoder);

934 break;

935 case AArch64::LDPWpost:

936 case AArch64::STPWpost:

937 case AArch64::LDPWpre:

938 case AArch64::STPWpre:

939 NeedsDisjointWritebackTransfer = true;

940 [[fallthrough]];

941 case AArch64::LDNPWi:

942 case AArch64::STNPWi:

943 case AArch64::LDPWi:

944 case AArch64::STPWi:

946 Decoder);

948 Decoder);

949 break;

950 case AArch64::LDNPQi:

951 case AArch64::STNPQi:

952 case AArch64::LDPQpost:

953 case AArch64::STPQpost:

954 case AArch64::LDPQi:

955 case AArch64::STPQi:

956 case AArch64::LDPQpre:

957 case AArch64::STPQpre:

958 case AArch64::LDTPQi:

959 case AArch64::LDTPQpost:

960 case AArch64::LDTPQpre:

961 case AArch64::LDTNPQi:

962 case AArch64::STTPQi:

963 case AArch64::STTPQpost:

964 case AArch64::STTPQpre:

965 case AArch64::STTNPQi:

967 Decoder);

969 Decoder);

970 break;

971 case AArch64::LDNPDi:

972 case AArch64::STNPDi:

973 case AArch64::LDPDpost:

974 case AArch64::STPDpost:

975 case AArch64::LDPDi:

976 case AArch64::STPDi:

977 case AArch64::LDPDpre:

978 case AArch64::STPDpre:

980 Decoder);

982 Decoder);

983 break;

984 case AArch64::LDNPSi:

985 case AArch64::STNPSi:

986 case AArch64::LDPSpost:

987 case AArch64::STPSpost:

988 case AArch64::LDPSi:

989 case AArch64::STPSi:

990 case AArch64::LDPSpre:

991 case AArch64::STPSpre:

993 Decoder);

995 Decoder);

996 break;

997 }

998

1000 Decoder);

1002

1003

1004 if (IsLoad && Rt == Rt2)

1006

1007

1008

1009 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))

1011

1013}

1014

1023

1025 default:

1026 return Fail;

1027 case AArch64::LDRAAwriteback:

1028 case AArch64::LDRABwriteback:

1030 Inst, Rn , Addr, Decoder);

1031 break;

1032 case AArch64::LDRAAindexed:

1033 case AArch64::LDRABindexed:

1034 break;

1035 }

1036

1038 Decoder);

1040 Decoder);

1042

1043 if (writeback && Rt == Rn && Rn != 31) {

1045 }

1046

1048}

1049

1057

1058 unsigned shift = extend & 0x7;

1059 if (shift > 4)

1060 return Fail;

1061

1063 default:

1064 return Fail;

1065 case AArch64::ADDWrx:

1066 case AArch64::SUBWrx:

1068 Decoder);

1070 Decoder);

1072 Decoder);

1073 break;

1074 case AArch64::ADDSWrx:

1075 case AArch64::SUBSWrx:

1077 Decoder);

1079 Decoder);

1081 Decoder);

1082 break;

1083 case AArch64::ADDXrx:

1084 case AArch64::SUBXrx:

1086 Decoder);

1088 Decoder);

1090 Decoder);

1091 break;

1092 case AArch64::ADDSXrx:

1093 case AArch64::SUBSXrx:

1095 Decoder);

1097 Decoder);

1099 Decoder);

1100 break;

1101 case AArch64::ADDXrx64:

1102 case AArch64::SUBXrx64:

1104 Decoder);

1106 Decoder);

1108 Decoder);

1109 break;

1110 case AArch64::SUBSXrx64:

1111 case AArch64::ADDSXrx64:

1113 Decoder);

1115 Decoder);

1117 Decoder);

1118 break;

1119 }

1120

1123}

1124

1131 unsigned imm;

1132

1133 if (Datasize) {

1134 if (Inst.getOpcode() == AArch64::ANDSXri)

1136 Decoder);

1137 else

1139 Inst, Rd, Addr, Decoder);

1141 Decoder);

1144 return Fail;

1145 } else {

1146 if (Inst.getOpcode() == AArch64::ANDSWri)

1148 Decoder);

1149 else

1151 Inst, Rd, Addr, Decoder);

1153 Decoder);

1156 return Fail;

1157 }

1160}

1161

1169

1170 if (Inst.getOpcode() == AArch64::MOVID)

1172 Decoder);

1173 else

1175 Decoder);

1176

1178

1180 default:

1181 break;

1182 case AArch64::MOVIv4i16:

1183 case AArch64::MOVIv8i16:

1184 case AArch64::MVNIv4i16:

1185 case AArch64::MVNIv8i16:

1186 case AArch64::MOVIv2i32:

1187 case AArch64::MOVIv4i32:

1188 case AArch64::MVNIv2i32:

1189 case AArch64::MVNIv4i32:

1191 break;

1192 case AArch64::MOVIv2s_msl:

1193 case AArch64::MOVIv4s_msl:

1194 case AArch64::MVNIv2s_msl:

1195 case AArch64::MVNIv4s_msl:

1197 break;

1198 }

1199

1201}

1202

1210

1211

1213 Decoder);

1215 Decoder);

1216

1219

1221}

1222

1229

1231 Decoder);

1234

1236}

1237

1246

1247 unsigned ShifterVal = (Imm >> 12) & 3;

1248 unsigned ImmVal = Imm & 0xFFF;

1249

1250 if (ShifterVal != 0 && ShifterVal != 1)

1251 return Fail;

1252

1253 if (Datasize) {

1254 if (Rd == 31 && !S)

1256 Inst, Rd, Addr, Decoder);

1257 else

1259 Decoder);

1261 Decoder);

1262 } else {

1263 if (Rd == 31 && !S)

1265 Inst, Rd, Addr, Decoder);

1266 else

1268 Decoder);

1270 Decoder);

1271 }

1272

1277}

1278

1289

1291 return Op1 == 0b000 && (Op2 == 0b000 ||

1292 Op2 == 0b001 ||

1293 Op2 == 0b010);

1294}

1295

1302 uint64_t pstate_field = (op1 << 3) | op2;

1303

1305 return Fail;

1306

1309

1310 auto PState = AArch64PState::lookupPStateImm0_15ByEncoding(pstate_field);

1311 if (PState &&

1314 return Fail;

1315}

1316

1324 uint64_t pstate_field = (crm_high << 6) | (op1 << 3) | op2;

1325

1327 return Fail;

1328

1331

1332 auto PState = AArch64PState::lookupPStateImm0_1ByEncoding(pstate_field);

1333 if (PState &&

1336 return Fail;

1337}

1338

1346

1349 Decoder);

1350 else

1352 Decoder);

1356

1358}

1359

1362 unsigned RegNo, uint64_t Addr,

1364

1365 if (RegNo & 0x1)

1366 return Fail;

1367

1368 MCRegister Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);

1371}

1372

1377 Inst, AArch64::WSeqPairsClassRegClassID, RegNo, Addr, Decoder);

1378}

1379

1384 Inst, AArch64::XSeqPairsClassRegClassID, RegNo, Addr, Decoder);

1385}

1386

1395 if (Rt != 0b11111)

1396 return Fail;

1397

1403 Decoder);

1404

1406}

1407

1414 return Fail;

1415

1416

1418 Decoder);

1419 if (Inst.getOpcode() != AArch64::DUPM_ZI)

1421 Decoder);

1424}

1425

1430

1431template

1434 if (Imm & ~((1LL << Bits) - 1))

1435 return Fail;

1436

1437

1438 if (Imm & (1 << (Bits - 1)))

1439 Imm |= ~((1LL << Bits) - 1);

1440

1443}

1444

1445

1446template

1449 unsigned Val = (uint8_t)Imm;

1450 unsigned Shift = (Imm & 0x100) ? 8 : 0;

1451 if (ElementWidth == 8 && Shift)

1452 return Fail;

1456}

1457

1458

1465

1468 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {

1471 }

1472 return Fail;

1473}

1474

1481

1482

1483

1484 if (Rd == Rs || Rs == Rn || Rd == Rn)

1486

1487

1488

1490 Inst, Rd, Addr, Decoder) ||

1492 Inst, Rs, Addr, Decoder) ||

1494 Inst, Rn, Addr, Decoder) ||

1496 Inst, Rd, Addr, Decoder) ||

1498 Inst, Rs, Addr, Decoder) ||

1500 Inst, Rn, Addr, Decoder))

1502

1504}

1505

1512

1513

1514

1515 if (Rd == Rm || Rm == Rn || Rd == Rn)

1517

1518

1519

1521 Inst, Rd, Addr, Decoder) ||

1523 Inst, Rn, Addr, Decoder) ||

1525 Inst, Rd, Addr, Decoder) ||

1527 Inst, Rn, Addr, Decoder) ||

1529 Inst, Rm, Addr, Decoder))

1531

1533}

1534

1540

1541

1542

1543 if (Rd == Rn)

1545

1546

1547

1549 Inst, Rd, Addr, Decoder) ||

1551 Inst, Rn, Addr, Decoder) ||

1553 Inst, Rd, Addr, Decoder) ||

1555 Inst, Rn, Addr, Decoder))

1557

1559}

1560

1564

1565

1566 unsigned Mask = 0x18;

1568 if ((Rt & Mask) == Mask)

1569 return Fail;

1570

1575

1578 Decoder);

1579

1581 default:

1582 return Fail;

1583 case AArch64::PRFMroW:

1585 Decoder);

1586 break;

1587 case AArch64::PRFMroX:

1589 Decoder);

1590 break;

1591 }

1592

1593 DecodeMemExtend(Inst, (Extend << 1) | Shift, Addr, Decoder);

1594

1596}

1597

1604

1607 Inst, RvBits, Addr, Decoder);

1610 Addr, Decoder);

1611

1612

1613

1616}

1617

1618#include "AArch64GenDisassemblerTables.inc"

1619#include "AArch64GenInstrInfo.inc"

1620

1627

1633

1635

1636 if (Bytes.size() < 4)

1637 return Fail;

1639

1640

1642 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);

1643

1644 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};

1645

1646 for (const auto *Table : Tables) {

1648 decodeInstruction(Table, MI, Insn, Address, this, STI);

1650 return Result;

1651 }

1652

1654}

1655

1658

1659

1660

1661 return 4;

1662}

1663

1668 std::unique_ptr &&RelInfo) {

1670 SymbolLookUp, DisInfo);

1671}

1672

static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1279

static DecodeStatus DecodeMPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:160

static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:214

static DecodeStatus DecodeMPR8RegisterClass(MCInst &Inst, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:145

static DecodeStatus DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1318

static DecodeStatus DecodeZPRMul2_MinMax(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:75

static DecodeStatus DecodeMPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:169

static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:357

static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:363

static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)

Definition AArch64Disassembler.cpp:1665

static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1475

static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:351

static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:488

static DecodeStatus DecodeMPRRegisterClass(MCInst &Inst, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:139

static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1203

static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:207

static DecodeStatus DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1297

static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1162

static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)

Definition AArch64Disassembler.cpp:1621

static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:60

static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:382

static DecodeStatus DecodeSETMemGoOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1535

static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1381

static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:757

static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:369

static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1339

static DecodeStatus DecodeZeroImm(MCInst &Inst, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1426

#define SoftFail

Definition AArch64Disassembler.cpp:44

static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1432

static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:333

static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:101

static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1223

static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)

Definition AArch64Disassembler.cpp:187

static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:850

static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:375

static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1459

static DecodeStatus DecodeMPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:151

static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)

Definition AArch64Disassembler.cpp:303

static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:198

static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:449

static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:315

static DecodeStatus DecodePCRelLabel9(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:240

static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)

Definition AArch64Disassembler.cpp:309

static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:345

static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1466

static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1374

static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:321

static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)

Definition AArch64Disassembler.cpp:112

static DecodeStatus DecodeSMESpillFillInstruction(MCInst &Inst, uint32_t Bits, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1599

static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1125

#define Fail

Definition AArch64Disassembler.cpp:43

MCDisassembler::DecodeStatus DecodeStatus

Definition AArch64Disassembler.cpp:36

static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:268

static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)

Definition AArch64Disassembler.cpp:88

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()

Definition AArch64Disassembler.cpp:1674

#define Success

Definition AArch64Disassembler.cpp:42

static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1506

static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1409

static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:250

static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:554

static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1015

static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1387

static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:276

static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1050

static bool isInvalidPState(uint64_t Op1, uint64_t Op2)

Definition AArch64Disassembler.cpp:1290

static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:47

static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:124

static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:339

static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:327

static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1447

static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1561

static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1238

static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:1361

static DecodeStatus DecodeMPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:178

static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:258

static DecodeStatus DecodeZTRRegisterClass(MCInst &Inst, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:133

static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)

Definition AArch64Disassembler.cpp:229

#define LLVM_EXTERNAL_VISIBILITY

MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override

Returns the disassembly of a single instruction.

Definition AArch64Disassembler.cpp:1628

uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const override

Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...

Definition AArch64Disassembler.cpp:1656

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

Context object for machine code objects.

Superclass for all disassemblers.

bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const

const MCSubtargetInfo & getSubtargetInfo() const

const MCSubtargetInfo & STI

raw_ostream * CommentStream

DecodeStatus

Ternary decode status.

Instances of this class represent a single low-level machine instruction.

unsigned getOpcode() const

void addOperand(const MCOperand Op)

const MCOperand & getOperand(unsigned i) const

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

Wrapper class representing physical registers. Should be passed by value.

Generic base class for all target subtargets.

const FeatureBitset & getFeatureBits() const

Symbolize and annotate disassembled instructions.

Wrapper class representing virtual and physical registers.

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

This class implements an extremely fast bulk output stream that can only output to a stream.

const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)

The type for the symbol lookup function.

int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)

The type for the operand information call back function.

static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)

isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...

std::enable_if_t< std::is_integral_v< IntType >, IntType > fieldFromInstruction(const IntType &Insn, unsigned StartBit, unsigned NumBits)

This is an optimization pass for GlobalISel generic memory operations.

Target & getTheAArch64beTarget()

Target & getTheAArch64leTarget()

Target & getTheAArch64_32Target()

Target & getTheARM64_32Target()

Target & getTheARM64Target()

constexpr int64_t SignExtend64(uint64_t x)

Sign-extend the number in the bottom B bits of X to a 64-bit integer.

static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)

RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.

static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)

RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.